REV. 0

AD7664

–5–

TO OUTPUT

PIN

1.6mA

500 A

1.4V

Figure 1. Load Circuit for Digital Interface Timing,

0.8V

2V

2V

0.8V

0.8V

2V

t

DELAY

t

DELAY

Figure 2. Voltage Reference Levels for Timing

PIN CONFIGURATION

48-Lead LQFP

(ST-48)

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44

39 38 37

43 42 41 40

PIN 1

IDENTIFIER

TOP VIEW

(Not to Scale)

AGND

CNVST

PD

RESET

CS

RD

DGND

AGND

AVDD

NC

DGND

OB/

2C

WARP

IMPULSE

NC = NO CONNECT

SER/

PAR

D0

D1

D2

BUSY

D15

D14

D13

AD7664

D3

D12

PIN FUNCTION DESCRIPTIONS

Pin

No.

Mnemonic

Type

Description

1

AGND

P

Analog Power Ground Pin.

2

AVDD

P

Input Analog Power Pins. Nominally 5 V.

3, 40–48

NC

No Connect.

4, 30

DGND

DI

Must Be Tied to Analog Ground.

5OB/

2C

DI

Straight Binary/Binary Two’s Complement. When OB/

2C is HIGH, the digital output is

straight binary; when LOW, the MSB is inverted resulting in a two’s complement output

from its internal shift register.

6

WARP

DI

Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode, the

maximum throughput is achievable, and a minimum conversion rate must be applied in order

to guarantee full specified accuracy. When LOW, full accuracy is maintained independent of

the minimum conversion rate.

7

IMPULSE

DI

Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode. In

this mode, the power dissipation is approximately proportional to the sampling rate.

8

SER/

PAR

DI

Serial/Parallel Selection Input. When LOW, the parallel port is selected; when HIGH, the

serial interface mode is selected and some bits of the DATA bus are used as a serial port.

9–12

DATA[0:3]

DO

Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs, regardless

of the state of SER/

PAR.

13

DATA[4]

DI/O

When SER/

PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output Bus.

or EXT/

INT

When SER/

PAR is HIGH, this input, part of the serial port, is used as a digital select input

for choosing the internal or an external data clock. With EXT/

INT tied LOW, the internal

clock is selected on SCLK output. With EXT/

INT set to a logic HIGH, output data is syn-

chronized to an external clock signal connected to the SCLK input.

14

DATA[5]

DI/O

When SER/

PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output Bus.

or INVSYNC

When SER/

PAR is HIGH, this input, part of the serial port, is used to select the active state

of the SYNC signal. It is active in both master and slave mode. When LOW, SYNC is active

HIGH. When HIGH, SYNC is active LOW.

15

DATA[6]

DI/O

When SER/

PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output Bus.

or INVSCLK

When SER/

PAR is HIGH, this input, part of the serial port, is used to invert the SCLK sig-

nal. It is active in both master and slave mode.