AD9765AST datasheet(15/28 Pages) AD

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REV. B

AD9765

–15–

AD9765

IOUTA

IOUTB

500

225

500

AD8047

COPT

Figure 34. DC Differential Coupling Using an Op Amp

The differential circuit shown in Figure 35 provides the neces-

sary level-shifting required in a single supply system. In this

case AVDD, which is the positive analog supply for both the

AD9765 and the op amp, is also used to level-shift the differ-

ential output of the AD9765 to midsupply (i.e., AVDD/2). The

AD8055 is a suitable op amp for this application.

AD9765

IOUTA

IOUTB

COPT

500

225

500

AD8055

AVDD

Figure 35. Single Supply DC Differential Coupled Circuit

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 36 shows the AD9765 configured to provide a unipolar

output range of approximately 0 V to +0.5 V for a doubly ter-

minated 50

Ω cable since the nominal full-scale current, I

OUTFS,

of 20 mA flows through the equivalent RLOAD of 25

Ω. In this

case, RLOAD represents the equivalent load resistance seen by

IOUTA or IOUTB. The unused output (IOUTA or IOUTB) can be

connected to ACOM directly or via a matching RLOAD. Differ-

ent values of IOUTFS and RLOAD can be selected as long as the

positive compliance range is adhered to. One additional con-

sideration in this mode is the integral nonlinearity (INL) as

discussed in the Analog Output section of this data sheet. For

optimum INL performance, the single-ended, buffered voltage

output configuration is suggested.

AD9765

IOUTA

IOUTB

VOUTA = 0 TO +0.5V

IOUTFS = 20mA

Figure 36. 0 V to 0.5 V Unbuffered Voltage Output

SINGLE-ENDED, BUFFERED VOLTAGE OUTPUT

CONFIGURATION

Figure 37 shows a buffered single-ended output configuration

in which the op amp U1 performs an I-V conversion on the

AD9765 output current. U1 maintains IOUTA (or IOUTB) at a

virtual ground, thus minimizing the nonlinear output imped-

ance effect on the DAC’s INL performance as discussed in

the Analog Output section. Although this single-ended con-

figuration typically provides the best dc linearity perform-

ance, its ac distortion performance at higher DAC update

rates may be limited by U1’s slewing capabilities. U1 pro-

vides a negative unipolar output voltage and its full-scale

output voltage is simply the product of RFB and IOUTFS. The

full-scale output should be set within U1’s voltage output

swing capabilities by scaling IOUTFS and/or RFB. An improve-

ment in ac distortion performance may result with a reduced

IOUTFS since the signal current U1 will be required to sink

will be subsequently reduced.

AD9765

IOUTA

IOUTB

COPT

200

VOUT = IOUTFS

RFB

IOUTFS = 10mA

RFB

200

Figure 37. Unipolar Buffered Voltage Output

POWER AND GROUNDING CONSIDERATIONS, POWER

SUPPLY REJECTION

Many applications seek high speed and high performance under

less than ideal operating conditions. In these application cir-

cuits, the implementation and construction of the printed circuit

board is as important as the circuit design. Proper RF tech-

niques must be used for device selection, placement and rout-

ing, as well as power supply bypassing and grounding to ensure

optimum performance. Figures 45 to 52 illustrate the recom-

mended printed circuit board ground, power and signal plane

layouts which are implemented on the AD9765 evaluation board.

One factor that can measurably affect system performance is the

ability of the DAC output to reject dc variations or ac noise

superimposed on the analog or digital dc power distribution.

This is referred to as the Power Supply Rejection Ratio. For dc

variations of the power supply, the resulting performance of the

DAC directly corresponds to a gain error associated with the

DAC’s full-scale current, IOUTFS. AC noise on the dc supplies is

common in applications where the power distribution is gener-

ated by a switching power supply. Typically, switching power

supply noise will occur over the spectrum from tens of kHz to

several MHz. The PSRR vs. frequency of the AD9765 AVDD

supply over this frequency range is shown in Figure 38.

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