AD9807JS datasheet(14/24 Pages) AD

14 / 24 page

AD9807/AD9805

–14–

REV. 0

3-Channel SHA Operation

This mode of the AD9807/AD9805 enables 3-channel simulta-

neous sampling; it differs from the CDS sampling mode in that

the CDS functions are replaced with sample-and-hold amplifiers

(SHAs). CDSCLK1 becomes the sample-and-hold clock;

CDSCLK2 is tied to ground. The input is sampled on the

falling edge of CDSCLK1. The input signals must be either dc

coupled and level shifted, or dc restored prior to driving the

VINR, VING, and VINB pins of the AD9807/AD9805 (clamp

mode must be disabled). The input signal in this mode is

ground-referenced. The offsets of the three input channels are

modified by the values stored in the input offset registers. The

part does not invert the input signals prior to amplification by

the PGAs; the settings in the corresponding PGA Gain Registers

determine the gains of the PGAs. These outputs from the

PGAs are then routed through a high speed multiplexer to a

12-bit A/D converter (10-bit for AD9805) for digitization; the

multiplexer cycles between the red, green and then blue

channels. After digitization, the data is modified by the amount

indicated in the Odd and Even Offset Registers. A digital

subtracter allows additional pixel rate offset modification of

each color based on the values written to the OFFSET data bus.

Finally, a digital multiplier allows pixel rate gain modification

of each color based on the values written to the GAIN data bus.

Latency for the red, green and blue channels is 6 ADCCLK

cycles (9 cycles for the gain and offset bus; see Figure 13).

The STRTLN signal indicates the first red, green and blue

pixels in a scan line and the red channel is always the first pixel

digitized. The state of STRTLN is evaluated on the rising

edges of ADCCLK. When STRTLN is low, the internal

circuitry is reset on the next rising edge of ADCCLK; the

multiplexer is switched to the red channel and the odd/even

circuitry is configured to expect even pixels. After STRTLN

goes high, the first set of pixels is assumed to be even. Consecu-

tive sets of pixels (red, green and blue) are assumed to alternate

between odd and even pixel sets.

1-Channel Operation with CDS

This mode of the AD9807/AD9805 enables single-channel, or

monochrome, sampling. The CCD waveform is ac coupled to

either the VINR, VING, and VINB pin of the AD9807/AD9805

where it is biased at an appropriate voltage level using the on-

chip clamp; the input may alternatively be dc coupled if it has

already been appropriately level shifted. Bits 6 and 7 in the

Configuration Register select the desired input. The internal

CDS takes two samples of the incoming pixel data: the first

sample (CDSCLK1) is taken during the reset time while the

second sample (CDSCLK2) is taken during the video, or data,

portion of the input pixel. The offset of the input signal is

modified by the value stored in the input offset register. The

voltage difference of the reset level and video level is inverted and

amplified by the PGA; the setting in the corresponding PGA

Gain Register determines the gain of the PGA. The output

from the PGA is then routed through a high-speed multiplexer

to a 12-bit A/D converter (10-bit for AD9805) for digitization;

the multiplexer does not cycle in this mode. After digitization,

the data is modified by the amount indicated in the Odd and

Even Offset Registers. A digital subtracter allows additional

pixel rate offset modification of the signal based on the values

written to the OFFSET data bus. Finally, a digital multiplier

allows pixel rate gain modification of the signal based on the

values written to the GAIN data bus. Latency is 6 ADCCLK

cycles (7 cycles for the gain and offset bus; see Figure 14).

The state of STRTLN is evaluated on the rising edges of

ADCCLK. When STRTLN is low, the internal circuitry is

reset on the next rising edge of ADCCLK; the odd/even

circuitry is configured to expect an even pixel. After STRTLN

goes high, the first pixel is assumed to be even. Consecutive

pixels (red, green or blue) are assumed to alternate between odd

and even. The blue and green channels are recommended for

single channel operation to achieve the maximum sampling rate;

if using red, invert ADCCLK as shown in Figure 1d.

1-Channel SHA Operation

This mode of the AD9807/AD9805 enables single-channel, or

monochrome sampling; it differs from the CDS monochrome

sampling mode in that the CDS function is replaced with a

sample-and-hold amplifier (SHA). CDSCLK1 becomes the

sample-and-hold clock; CDSCLK2 is tied to ground. The

input is sampled on the falling edge of CDSCLK1. The input

waveform would typically be either dc coupled and level shifted,

or dc restored prior to driving either the VINR, VING and

VINB pins of the AD9807/AD9805 (clamp mode must be

disabled).

Bits 6 and 7 in the Configuration Register select the desired

input. The input signal in this mode is ground referenced. The

input signal is not inverted prior to amplification by the PGA;

the setting in the corresponding PGA Gain Register determines

the gain of the PGA. The offset of the input signal is modified

by the value stored in the input offset register. This signal is

then routed through a high speed multiplexer to a 12-bit A/D

converter (10-bit for AD9805) for digitization; the multiplexer

does not cycle in this mode. After digitization, the data is

modified by the amount indicated in the Odd and Even Offset

Registers. A digital subtracter allows additional pixel rate offset

modification of the signal based on the values written to the

OFFSET data bus. Finally, a digital multiplier allows pixel rate

gain modification of the signal based on the values written to the

GAIN data bus. Latency is 6 ADCCLK cycles (7 cycles for

gain and offset; see Figure 15).

The state of STRTLN is evaluated on the rising edges of

ADCCLK. When STRTLN is low, the internal circuitry is

reset on the next rising edge of ADCCLK; the odd/even

circuitry is configured to expect an even pixel. After STRTLN

goes high, the first pixel is assumed to be even. Consecutive

pixels (red, green or blue) are assumed to alternate between odd

and even. The blue and green channels are recommended for

single channel operation to achieve the maximum sampling rate;

if using red, invert ADCCLK as shown in Figure 1f.

2-Channel Bayer Mode Operation with CDS

This mode of the AD9807/AD9805 enables Bayer Mode. The

CCD waveform is ac coupled to both the VING and VINB pins

of the AD9807/AD9805 where it is biased at an appropriate

voltage level using the on-chip clamp; the input may alterna-

tively be dc coupled if it has already been appropriately level

shifted. The internal CDS takes two samples of the incoming

pixel data: the first sample (CDSCLK1) is taken during the

reset time while the second sample (CDSCLK2) is taken during

the video, or data, portion of the input pixel. The offset of the

input signal is modified by the value stored in the input offset

AD9807JS Datasheet(PDF) 14 Page - Analog Devices

AD9807JS Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

Datasheet Descarga

Enlace URL