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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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AD9805JS Datasheet(PDF) 4 Page - Analog Devices |
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AD9805JS Datasheet(HTML) 4 Page - Analog Devices |
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4 / 24 page  AD9807/AD9805 –4– REV. 0 TIMING SPECIFICATIONS Parameter Symbol Min Typ Max Units CLOCK PARAMETERS 3-Channel Conversion Rate tCRA 500 ns 1-Channel Conversion Rate tCRB 166 ns CDSCK1 Pulse Width tC1A 30 ns CDSCK1 Pulse Width tC1B 30 ns CDSCK2 Pulse Width tC2A 30 ns CDSCK2 Pulse Width tC2B 30 ns CDS Clocks Digital Quiet Time tQ 20 ns CDSCK2 Falling to CDSCK1 Rising tC2C1A 80 ns CDSCK2 Falling to CDSCK1 Rising tC2C1B 40 ns CDSCK1 Falling to CDSCK2 Rising tC1C2A 20 ns CDSCK1 Falling to CDSCK2 Rising tC1C2B 20 ns ADCCLK Rising to CDSCK1 Falling tC1AD 35 ns ADCCLK Pulse Width tACLK 50 ns ADCCLK Period tCP 166 ns ADCCLK Period (Red Single Channel Mode) tCP2 200 ns 3-Channel Settling Time tSTL1 60 ns 1-Channel Settling Time (B and G Only) tSTL2 30 ns ADCCLK Rising to Control Data Setup tGOS 15 ns ADCCLK Rising to Control Data Hold tGOH 15 ns STRTLN Rising, Falling Setup tS 15 ns STRTLN Rising, Falling Hold tH 15 ns Aperture Delay tAD 10 ns REGISTER WRITE/READ Address Setup Time tAS 15 ns Address Hold Time tAH 15 ns Data Setup Time tDS 15 ns Data Hold Time tDH 15 ns Chip Select Setup Time tCSS 15 ns Chip Select Hold Time tCSH 15 ns Write Pulse Width tPWW 25 ns Read Pulse Width tPWR 50 ns Read To Data Valid tDD 40 ns DATA OUTPUT Output Delay tOD 15 ns 3-State to Data Valid tEDV 15 ns Output Enable High to 3-State tHZ 5ns Latency 6 ADCCLK Cycles (TMIN to TMAX with AVDD = +5.0 V, DVDD = +5.0 V, unless otherwise noted) Table I. Output Controls CSB 00 000 011 RDB 00 111 1x x WRB 01 001 1x x OEB x x 010 101 DOUT XQ XD X Z Q Z MPU MPU ADC LEGEND: x = Don't Care X = Unknown (Not Recommended) Q = Outputs D = Inputs Z = 3-State |
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