AD9832 datasheet(12/16 Pages) AD

12 / 16 page

AD9832

–12–

REV. A

DATA WRITE**

FREG<0> = fOUT0/fMCLK*232

FREG<1> = fOUT1/fMCLK*232

PHASEREG <3:0> = DELTA PHASE<0, 1, 2, 3>

SELECT DATA SOURCES***

SET FSELECT

SET PSEL0, PSEL1

INITIALIZATION*

WAIT 6 MCLK CYCLES (8 MCLK CYCLES IF SYNC = 1)

DAC OUTPUT

VOUT = VREFIN*6.25*ROUT/RSET*(1 + SIN(2 (FREG*fMCLK*t/232 + PHASEREG/212)))

CHANGE PHASE?

CHANGE fOUT?

YES

CHANGE fOUT?

YES

CHANGE FSELECT

CHANGE PHASEREG?

YES

CHANGE PSEL0, PSEL1

Figure 22. Flow Chart for AD9832 Initialization and Operation

INITIALIZATION*

CONTROL REGISTER WRITE

SET SLEEP

RESET = 1

CLR = 1

SET SYNC AND/OR SELSRC TO 1

YES

CONTROL REGISTER WRITE

SYNC = 1

AND/OR

SELSRC = 1

WRITE INITIAL DATA

FREG<0> = fOUT0/fMCLK*2

FREG<1> = fOUT1/fMCLK*2

PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3>

SET PINS OR FREQUENCY/PHASE REGISTER WRITE

SET FSELECT, PSEL0 AND PSEL1

CONTROL REGISTER WRITE

SLEEP = 0

RESET = 0

CLR = 0

Figure 23. Initialization

DATA WRITE**

DEFERRED TRANSFER WRITE

WRITE 8 BITS TO DEFER REGISTER

DIRECT TRANSFER WRITE

WRITE PRESENT 8 BITS AND 8 BITS IN

DEFER REGISTER TO DATA REGISTER

WRITE ANOTHER WORD TO THIS

WRITE A WORD TO ANOTHER REGISTER

CHANGE 8 BITS ONLY

YES

CHANGE 16 BITS

YES

Figure 24. Data Writes

SELECT DATA SOURCES***

FSELECT/PSEL PINS BEING USED?

YES

SELSRC = 0

SET PINS

SET FSELECT

SET PSEL0

SET PSEL1

FREQUENCY/PHASE REGISTER WRITE

SET FSELECT

SET PSEL0

SET PSEL1

SELSRC = 1

Figure 25. Selecting Data Sources

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