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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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ADM1024ARU Datasheet(PDF) 26 Page - Analog Devices |
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ADM1024ARU Datasheet(HTML) 26 Page - Analog Devices |
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26 / 28 page  ADM1024 –26– REV. 0 Table XII. Register 43h, INT Interrupt Mask Register 1 (Power-On Default = 00h) Bit Name R/ W Description 0 2.5 V/Ext. Temp2 Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 1VCCP1 Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 2VCC Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 3 5 V Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 4 Int. Temp Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 5 Ext. Temp1 Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 6 FAN1/AIN1 Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 7 FAN2/AIN2 Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. Table XIII. Register 44h, INT Mask Register 2 (Power-On Default = 00h) Bit Name R/ W Description 0 12 V Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 1VCCP2 Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 2 Reserved Read/ Write Power-up default set to Low. 3 Reserved Read/ Write Power-up default set to Low. 4 CI Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 5 THERM (Input) Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 6 D1 Fault Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. 7 D2 Fault Read/ Write A one disables the corresponding interrupt status bit for INT interrupt. Table XIV. Register 46h, Chassis Intrusion Clear (Power-On Default = 00h) Bit Name R/ W Description 0–6 Reserved Read Only Undefined, always reads as 00h. 7 Chassis Int. Clear Read/ Write A one outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The register bit clears itself after the pulse has been output. Table XV. Register 47h, VID0–3/FAN Divisor Register (Power-On Default 0101(VID3–0)) Bit Name R/ W Description 0–3 VID Read The VID[3:0] inputs from processor core power supplies to indicate the operating voltage (e.g., 1.3 V to 3.5 V) 4–5 FAN1 Divisor Read/ Write Sets counter prescaler for FAN1 speed measurement <5:4> = 00 – divide by 1 <5:4> = 01 – divide by 2 <5:4> = 10 – divide by 4 <5:4> = 11 – divide by 8. 6–7 FAN2 Divisor Read/ Write Sets counter prescaler for FAN2 speed measurement <7:6> = 00 – divide by 1 <7:6> = 01 – divide by 2 <7:6> = 10 – divide by 4 <7:6> = 11 – divide by 8. Table XVI. Register 49h, VID4/Device ID Register (Power-On Default 1000000(VID4)) Bit Name R/ W Description 0 VID4 Read Only VID4 Input from Pentium. 1–7 Reserved Read Only Undefined, always reads as 1000 000(VID4). |
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