DAC08

–11–

REV. A

MULTIPLYING OPERATION

The DAC08 provides excellent multiplying performance with an

of 4 mA to 4 mA. Monotonic operation is maintained over a

µA to 4.0 mA.

SETTLING TIME

The DAC08 is capable of extremely fast settling times, typically

board layout must be employed to obtain full performance po-

tential during testing and application. The logic switch design

enables propagation delays of only 35 ns for each of the 8 bits.

Settling time to within 1/2 LSB of the LSB is therefore 35 ns,

with each progressively larger bit taking successively longer. The

MSB settles in 85 ns, thus determining the overall settling time

of 85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns.

The output capacitance of the DAC08 including the package is

approximately 15 pF, therefore the output RC time constant

Settling time and propagation delay are relatively insensitive to

logic input amplitude and rise and fall times, due to the high

gain of the logic switches. Settling time also remains essentially

values lies in the ability to attain a given output level with lower

load resistors, thus reducing the output RC time constant.

Measurement of settling time requires the ability to accurately

resolve

±4 µA, therefore a 1 kΩ load is needed to provide ad-

equate drive for most oscilloscopes. The settling time fixture

shown in schematic labelled “Settling Time Measurement” uses

a cascode design to permit driving a 1 k

Ω load with less than

values of less than 1.0 mA, excessive RC damping of the output

is difficult to prevent while maintaining adequate sensitivity.

However, the major carry from 01111111 to 10000000 provides

an accurate indicator of settling time. This code change does

not require the normal 6.2 time constants to settle to within

±0.2% of the final value, and thus settling times may be ob-

DAC08 switching transients or “glitches” are very low and may

be further reduced by small capacitive loads at the output at a

minor sacrifice in settling time.

Fastest operation can be obtained by using short leads, minimiz-

ing output capacitance and load resistor values, and by adequate

do not require large electrolytic bypass capacitors as the supply

current drain is independent of input logic states; 0.1

µF capaci-

tors at the supply pins provide full transient protection.

Figure 30. Settling Time Measurement