DAC312

–4–

REV. C

WAFER TEST LIMITS

DAC312N

DAC312G

Parameter

Symbol

Conditions

Limit

Limit

Units

Resolution

12

12

Bits min

Monotonicity

12

12

Bits min

Nonlinearity

±0.05

±0.05

%FS max

Output Voltage

Full-Scale Current

+10

+10

V max

Compliance

Voc

Change <1/2 LSB

–5

–5

V min

Full-Scale

4.031

4.063

mA max

Current

3.967

3.935

mA min

Full-Scale Symmetry

±1

±2

µA max

Zero-Scale Current

0.1

0.1

µA max

Differential

DNL

Deviation from

±0.012

±0.025

%FS max

Nonlinearity

Ideal Step Size

±1/2

±1

Bits (LSB) max

Logic Input Levels “0”

0.8

0.8

V max

Logic Input Levels “1”

2

2

V min

Logic Input Swing

+18

+18

V max

–5

–5

V min

Reference Bias

Current

–2

–2

µA max

Power Supply

V+ = +13.5 V to +16.5 V, V– = –15 V

±0.001

±0.001

Sensitivity

V– = –13.5 V to –16.5 V, V+ = +15 V

±0.001

±0.001

%/%max

Power Supply

I+

7

7

Current

I–

–18

–18

mA max

Power

Dissipation

375

375

mW max

NOTE

Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed

for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.

DICE CHARACTERISTICS

DIE SIZE 0.141

× 0.096 inch, 13,536 sq. mils (3.58 × 2.44 mm, 8.74 sq. mm)

1. B1 (MSB)

11. B11

2. B2

12. B12 (LSB)

3. B3

4. B4

5. B5

6. B6

16. COMP

7. B7

17. V–

8. B8

9. B9

10. B10

20. V+