Data Sheet

ADP7182

Rev. A | Page 27 of 28

OUTLINE DIMENSIONS

PIN 1

INDICATOR

(R 0.2)

BOTTOM VIEW

TOP VIEW

1

4

8

5

INDEX

AREA

SEATING

PLANE

0.80

0.75

0.70

0.30

0.25

0.18

0.05 MAX

0.02 NOM

0.80 MAX

0.55 NOM

0.20 REF

0.50 BSC

COPLANARITY

0.08

2.48

2.38

2.23

1.74

1.64

1.49

0.50

0.40

0.30

COMPLIANT

TO JEDEC STANDARDS MO-229-WEED-4

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

SECTION OF THIS DATA SHEET.

0.20 MIN

EXPOSED

PAD

3.10

3.00 SQ

2.90

Figure 97. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]

3 mm × 3 mm Body, Very Very Thin, Dual Lead

(CP-8-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model1

Temperature Range

Output Voltage (V)2

Package Description

Package Option

Branding

ADP7182ACPZ-R7

−40°C to +125°C

Adjustable

8-Lead LFCSP_WD

CP-8-5

LN6

ADP7182ACPZ-5.0-R7

−40°C to +125°C

−5

8-Lead LFCSP_WD

CP-8-5

LN9

ADP7182CP-EVALZ

Evaluation Board

1

Z = RoHS Compliant Part.

2

For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.