ADRF6518ACPZ-R7 datasheet(4/36 Pages) AD

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ADRF6518

Preliminary Technical Data

Rev. PrA | Page 4 of 36

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

NOISE/DISTORTION

Corner Frequency = 31 MHz

Output Noise Density

Maximum gain at fC/2

−105.5

dBV/Hz

Minimum gain at fC/2

−105.5

dBV/Hz

Second Harmonic, HD2

10 MHz fundamental, 1.5 V p-p at VGA1 output

voltage

VGA2, VGA3 at minimum gain (digital and

analog)

dBc

Third Harmonic, HD3

10 MHz fundamental, 1.5 V p-p at VGA1 output

voltage

VGA2, VGA3 at minimum gain (digital and

analog)

dBc

IMD3

f1 = 500 kHz, f2 = 550 kHz, 1.5 V p-p composite

output voltage

dBc

Corner Frequency = 63 MHz

Output Noise Density

Minimum gain

−105.5

dBV/Hz

Maximum gain

−105.5

dBV/Hz

Second Harmonic, HD2

20 MHz fundamental, 1.5 V p-p at VGA1 output

voltage

VGA2, VGA3 at minimum gain (digital and

analog)

dBc

Third Harmonic, HD3

20 MHz fundamental, 1.5 V p-p at VGA1 output

voltage

VGA2, VGA3 at minimum gain (digital and

analog)

dBc

DIGITAL LOGIC

LE, CLK, DATA, SDO

Input High Voltage, VINH

Input Low Voltage, VINL

<0.8

Input Current, IINH/IINL

µA

Input Capacitance, CIN

SPI TIMING

LE, CLK, DATA, SDO

fSCLK

1/tSCLK

MHz

tDH

DATA hold time

tDS

DATA setup time

tLH

LE hold time

tLS

LE setup time

tPW

CLK high pulse width

CLK to SDO delay

POWER AND ENABLE

VPS, VPSD, COM, COMD, ENBL

Supply Voltage Range

3.15

3.3

3.45

Total Supply Current

ENBL = 5 V

Maximum BW setting, high power filter

400

Minimum BW setting, low power filter

360

Filter Bypassed, high power mode

260

Filter Bypassed, low power mode

230

Disable Current

ENBL = 0 V

Disable Threshold

1.6

Enable Response Time

Delay following ENBL low-to-high transition

µs

Disable Response Time

Delay following ENBL high-to-low transition

300

ADRF6518ACPZ-R7 Datasheet(PDF) 4 Page - Analog Devices

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