OMAP3530ECBC72 datasheet(164/264 Pages) TI1

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OMAP3530/25 Applications Processor

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

www.ti.com

Table 6-6. GPMC/NOR Flash Interface Asynchronous Timing – Internal Parameters (continued)

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

FI4

Maximum address generation delay from internal

6.5

9.1

13.7

functional clock

FI5

Maximum address valid generation delay from internal

6.5

9.1

13.7

functional clock

FI6

Maximum byte enable generation delay from internal

6.5

9.1

13.7

functional clock

FI7

Maximum output enable generation delay from internal

6.5

9.1

13.7

functional clock

FI8

Maximum write enable generation delay from internal

6.5

9.1

13.7

functional clock

FI9

Maximum functional clock skew

100

170

200

Table 6-7. GPMC/NOR Flash Interface Timing Requirements – Asynchronous Mode

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

FA5(1)

tacc(DAT)

Data maximum access

H(2)

GPMC_FCLK cycles

time

FA20(3)

tacc1-pgmode(DAT) Page mode successive

P(4)

GPMC_FCLK cycles

data maximum access

time

FA21(5)

tacc2-pgmode(DAT) Page mode first data

H(2)

GPMC_FCLK cycles

maximum access time

(1)

The FA5 parameter illustrates the amount of time required to internally sample input Data. It is expressed in number of GPMC functional

clock cycles. From start of read cycle and after FA5 functional clock cycles, input Data is internally sampled by active functional clock

edge. FA5 value must be stored inside the AccessTime register bit field.

(2)

H = AccessTime * (TimeParaGranularity + 1)

(3)

The FA20 parameter illustrates amount of time required to internally sample successive input Page Data. It is expressed in number of

GPMC functional clock cycles. After each access to input Page Data, next input Page Data is internally sampled by active functional

clock edge after FA20 functional clock cycles. The FA20 value must be stored in the PageBurstAccessTime register bit field.

(4)

P = PageBurstAccessTime * (TimeParaGranularity + 1)

(5)

The FA21 parameter illustrates amount of time required to internally sample first input Page Data. It is expressed in number of GPMC

functional clock cycles. From start of read cycle and after FA21 functional clock cycles, First input Page Data is internally sampled by

active functional clock edge. FA21 value must be stored inside the AccessTime register bit field.

Table 6-8. GPMC/NOR Flash Interface Switching Characteristics – Asynchronous Mode

NO.

PARAMETER

1.15 V

1.0 V

0.9 V

UNIT

MIN

MAX

MIN

MAX

MIN

MAX

tR(DO)

Rise time, output data

2.0

tF(DO)

Fall time, output data

2.0

FA0

tW(nBEV)

Pulse duration,

Read

N(12)

gpmc_nbe0_cl

Write

N(12)

e, gpmc_nbe1

valid time

FA1

tW(nCSV)

Pulse duration,

Read

A(1)

gpmc_ncsx(13)

Write

A(1)

v low

FA3

td(nCSV-nADVIV)

Delay time,

Read

B(2) – 0.2

B(2) + 2.0

B(2) – 0.2

B(2) + 2.6

B(2) – 0.2

B(2) + 3.7

gpmc_ncsx(13)

Write

B(2) – 0.2

B(2) + 2.0

B(2) – 0.2

B(2) + 2.6

B(2) – 0.2

B(2) + 3.7

valid to

gpmc_nadv_al

e invalid

FA4

td(nCSV-nOEIV)

Delay time,

C(3) – 0.2

C(3) + 2.0

C(3) – 0.2

C(3) + 2.6

C(3) – 0.2

C(3) + 3.7

gpmc_ncsx(13) valid to

gpmc_noe invalid

(Single read)

TIMING REQUIREMENTS AND SWITCHING CHARACTERISTICS

164

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