OMAP3530ECBC72 datasheet(141/264 Pages) TI1

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4.3 DPLL and DLL Specifications

OMAP

DLL

vdds_dpll_dll

PowerRail

DPLL4

DPLL1

DPLL2

DPLL3

vdds_dpll_per

DPLL5

030-016

4.3.1

Digital Phase-Locked Loop (DPLL)

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

The OMAP3530/25 integrates seven DPLLs and a DLL. The PRM and CM drive five of them, while the

sixth (not supported) and the seventh (not supported) are controlled by the display subsystem.

The five main DPLLs are:

• DPLL1 (MPU)

• DPLL2 (IVA2)

• DPLL3 (Core)

• DPLL4 (Peripherals)

• DPLL5 (Second Peripherals DPLL)

Figure 4-9 illustrates the DLL and DPLL implementation.

(1)

Figure 4-9. DPLL and DLL Implementation

For more information on the OMAP3530/25 Applications Processor DPLLs and clocking structure, see the

Power, Reset, and Clock management (PRCM) chapter of the OMAP35x Applications Processor TRM

(literature number SPRUFA5).

The DPLL provides all interface clocks and some functional clocks (such as the processor clocks) of the

OMAP3530/25 device.

DPLL1 and DPLL2 get an always-on clock used to produce the synthesized clock. They get a high-speed

bypass clock used to switch the DPLL output clock on this high-speed clock during bypass mode.

The high-speed bypass clock is an L3 divided clock (programmable by 1 or 2) that saves DPLL processor

power consumption when the processor does not need to run faster than the L3 clock speed, or optimizes

performance during frequency scaling.

Each DPLL synthesized frequency is set by programming M (multiplier) and N (divider) factors. In addition,

all DPLL outputs can be controlled by an independent divider (M2 to M6).

The clock generating DPLLs of the OMAP3530/25 device have following features:

• Independent power domain per DPLL

• Controlled by clock-manager (CM)

• Fed with always-on system clock with independent gating control per DPLL

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CLOCK SPECIFICATIONS

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