OMAP3530ECBC72 datasheet(143/264 Pages) TI1

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4.3.3

DPLLs and DLL Characteristics

OMAP3530/25 Applications Processor

www.ti.com

SPRS507F – FEBRUARY 2008 – REVISED OCTOBER 2009

Several specifications characterize the seven DPLLs.

Table 4-14 summarizes the DPLL characteristics and assumes testing over recommended operating

conditions.

Table 4-14. DPLL Characteristics

NAME

PARAMETER

MIN

TYP

MAX

UNIT

COMMENTS(1)

vdds_dpll_per

1.71

1.8

1.89

At ball level (+5%, +10%)

vdds_dpll_dll

1.71

1.8

1.89

Junction temperature

–40

105

°C

Will not unlock after lock over this range for

slow temperature drifts

finput

Input reference frequency(2)

0.75

MHz

FINP

finternal

Internal reference frequency

0.75

2.1

MHz

FREQSEL3 = 0; FINT = FINP/(N+1)

7.5

MHz

FREQSEL3 = 1; FINT = FINP/(N+1)

foutput

CLKOUT output frequency

900

MHz

foutput*2

CLKOUTx2 output

1800

MHz

frequency

tlock

Frequency lock time(3)

71.4

200

µs

150 FINT cycles; FREQSEL3 = 0

37.1

104

µs

780 FINT cycles; FREQSEL3 = 1

plock

Phase lock time

166.7

466.7

µs

350 FINT cycles; FREQSEL3 = 0

46.7

130.7

µs

980 FINT cycles; FREQSEL3 = 1

trelock

Relock time – frequency

4.8

13.3

µs

10 FINT cycles

lock(4)

Lowcurrstby = 0; FREQSEL3 = 0

4.8

13.3

µs

100 FINT cycles

Lowcurrstby = 0; FREQSEL3 = 1

53.3

µs

40 FINT cycles

Lowcurrstby = 1; FREQSEL3 = 0

53.3

µs

400 FINT cycles

Lowcurrstby = 1; FREQSEL3 = 1

prelock

Relock time – Phase lock(4)

71.4

200

µs

150 FINT cycles

Lowcurrstby = 0; FREQSEL3 = 0

11.9

33.3

µs

250 FINT cycles

Lowcurrstby = 0; FREQSEL3 = 1

95.2

266.7

µs

200 FINT cycles

Lowcurrstby = 1; FREQSEL3 = 0

26.7

74.7

µs

560 FINT cycles

Lowcurrstby = 1; FREQSEL3 = 1

and Table 4-16 show the DPLL1 and DPLL2 clock frequency ranges.

Note: The DPLL1 and DPLL2 clock frequency ranges depend on the VDD1 (vdd_mpu_iva) operating point.

(1)

freqsel needs to be programmed accordingly to reference clock and DPLL divider (register setting), Lowcurrstdby depends on the targeted

DPLL power state (dynamic).

Lowcurrstdby = 0 then DPLL is in normal mode

Lowcurrstdby = 1 then DPLL is in low-power mode

(2)

Input frequencies below 0.75 MHz are possible with performance penalty.

(3)

Maximum frequency for nominal conditions. Speed binning possible above fmax.

(4)

Relock time assumes typical operating conditions, 4

°C maximum temperature drift (see the Functional Specification for more detailed

information).

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