8403A datasheet(21/32 Pages) AD

21 / 32 page

AD8400/AD8402/AD8403

Rev. E | Page 21 of 32

Like a mechanical potentiometer, RDAC is symmetrical. The

resistance between the Wiper W and Terminal A also produces

a digitally controlled complementary resistance, RWA. When

these terminals are used, the B terminal can be tied to the wiper

or left floating. RWA starts at the maximum and decreases as the

data loaded into the RDAC latch increases. The general transfer

equation for this RWA is

()

−

256

(3)

where D is the data loaded into the 8-bit RDAC# latch, and RAB

is the nominal end-to-end resistance.

For example, when the B terminal is either open-circuited or

tied to the Wiper W, the following RDAC latch codes result in

the following RWA (for the 10 kΩ version):

Table 11.

D (Dec)

RWA (

Ω)

Output State

255

Full-Scale

128

5,050

Midscale (RS = 0 Condition)

10,011

1 LSB

10,050

Zero-Scale

The typical distribution of RAB from channel to channel

matches within ±1%. However, device-to-device matching

is process lot dependent and has a ±20% variation. The tem-

perature coefficient, or the change in RAB with temperature,

is 500 ppm/°C.

The wiper-to-end-terminal resistance temperature coefficient

has the best performance over the 10% to 100% of adjustment

range where the internal wiper contact switches do not con-

tribute any significant temperature related errors. The graph in

Figure 18 shows the performance of RWB tempco vs. code. Using

the potentiometer with codes below 32 results in the larger

temperature coefficients plotted.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates an output voltage

proportional to the input voltage applied to a given terminal.

For example, connecting the A terminal to 5 V and the B termi-

nal to ground produces an output voltage at the wiper starting

at 0 V up to 1 LSB less than 5 V. Each LSB is equal to the voltage

applied across the A to B terminals divided by the 256-position

resolution of the potentiometer divider. The general equation

defining the output voltage with respect to ground for any given

input voltage applied to the A to B terminals is

256

(4)

Operation of the digital potentiometer in the voltage divider

mode results in more accurate operation over temperature.

Here the output voltage is dependent on the ratio of the internal

resistors, not the absolute value; therefore, the temperature drift

improves to 15 ppm/°C.

At the lower wiper position settings, the potentiometer divider

temperature coefficient increases because the contribution of

the CMOS switch wiper resistance becomes an appreciable

portion of the total resistance from the B terminal to the

Wiper W. See Figure 17 for a plot of potentiometer tempco

performance vs. code setting.

DIGITAL INTERFACING

The AD8400/AD8402/AD8403 contain a standard SPI-

compatible, 3-wire, serial input control interface. The three

inputs are clock (CLK), chip select (CS), and serial data input

(SDI). The positive-edge sensitive CLK input requires clean

transitions to avoid clocking incorrect data into the serial input

1 V/μs. Standard logic families work well. If mechanical switches

are used for product evaluation, they should be debounced by

a flip-flop or other suitable means. The block diagrams in

, and

show the internal digital

circuitry in more detail. When

Figure 46 Figure 47

Figure 48

CS is taken active low, the clock

loads data into the 10-bit serial register on each positive clock

edge (see

Table 12

RDAC

LATCH

NO. 1

GND

VDD

AD8400

CLK

ADDR

DEC

SDI

10-BIT

SER

REG

Figure 46. AD8400 Block Diagram

RDAC

LATCH

NO. 1

AGND

VDD

AD8402

CLK

RDAC

LATCH

NO. 2

ADDR

DEC

SDI

10-BIT

SER

REG

SHDN

DGND

Figure 47. AD8402 Block Diagram

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