Advanced Power

Electronics Corp.

APE1920

APPLICATION INFORMATION

Under Voltage Lockout (UVLO)

Input Capacitor Selection

Output Capacitor Selection

Layout Guide

(1) MESOP-10/TDFN 3x3-10L

7

To avoid mis-operation of the device at low input voltages an under voltage lockout is included that disables

the device, if the input voltage falls below (2.35V-150mV).

For better input bypassing, low-ESR ceramic capacitors are recommended for performance. Two parallel

10uF (or one 22uF) input capacitor is sufficient for most applications. For a lower output power requirement

application, this value can be decreased.

For lower output voltage ripple, low-ESR output capacitor like ceramic capacitor is recommended. Three

parallel 10uF ceramic capacitors work for most of the applications. Higher capacitor values can be used to

improve the load transient response and reduce output ripple.

C2 must be placed between VIN and

PGND as closer as possible, VIN trace

should be wide and short. The PGND

trace can not directly connect to SGND,

the trace take a via to ground area of

bottom.

LX should connected to lnductor by wide and

short trace, keep sensitive components away

from this trace.

R2 and C8 should be connected

to FB pin by short trace.

APE1920MM10/APE1920TGN3

VIN

C2

L1

GND

VOUT

LX

SGND

VCC

PGND

SS

FREQ

EN

1

2

3

4

5

6

7

8

9

10

LX

FB

COMP

Expose

Pad

VCC

C4

R3

C6

C7

R6

R8

R2

C5

R4

D1

C3

R7

GND

C4 must be placed between VCC pin

and SGND as closer as possible. The

SGND must connect to exposed pad

directly.

Frequency Selection, if FREQ connect to VCC,

the frequency is 1.2MHz, else connect R7 to

GND, the frequency is 680KHz.

C1