DAC08CS datasheet(14/20 Pages) AD

14 / 20 page

DAC08

Rev. C | Page 14 of 20

Fastest settling times are obtained when Pin 1 sees a low

impedance. If Pin 1 is connected to a 1 kΩ divider, for example,

it should be bypassed to ground by a 0.01 µF capacitor.

ANALOG OUTPUT CURRENTS

Both true and complemented output sink currents are provided

where IO + IO = IFS. Current appears at the true (IO) output when

a 1 (logic high) is applied to each logic input. As the binary

count increases, the sink current at Pin 4 increases proportionally,

in the fashion of a positive logic DAC. When a 0 is applied to

any input bit, that current is turned off at Pin 4 and turned on at

Pin 2. A decreasing logic count increases IO as in a negative or

inverted logic DAC. Both outputs may be used simultaneously.

If one of the outputs is not required, it must be connected to

ground or to a point capable of sourcing IFS; do not leave an

unused output pin open.

Both outputs have an extremely wide voltage compliance

enabling fast direct current-to-voltage conversion through a

resistor tied to ground or other voltage source. Positive compli-

ance is 36 V above V− and is independent of the positive supply.

Negative compliance is given by

V− + (IREF × 1 kΩ) + 2.5 V

The dual outputs enable double the usual peak-to-peak load

swing when driving loads in quasi-differential fashion. This

feature is especially useful in cable driving, CRT deflection and

in other balanced applications such as driving center-tapped

coils and transformers.

POWER SUPPLIES

The DAC08 operates over a wide range of power supply

voltages from a total supply of 9 V to 36 V. When operating at

supplies of ±5 V or lower, IREF ≤ 1 mA is recommended. Low

reference current operation decreases power consumption and

increases negative compliance (Figure 11), reference amplifier

negative common-mode range (Figure 14), negative logic input

range (Figure 15), and negative logic threshold range (Figure 16).

For example, operation at −4.5 V with IREF = 2 mA is not

recommended because negative output compliance would be

reduced to near zero. Operation from lower supplies is possible;

however, at least 8 V total must be applied to ensure turn-on of

the internal bias network.

Symmetrical supplies are not required, as the DAC08 is quite

insensitive to variations in supply voltage. Battery operation is

feasible because no ground connection is required: however, an

artificial ground may be used to ensure logic swings, etc., remain

between acceptable limits. Power consumption is calculated as

follows:

() (

) ( ) (

)

−

A useful feature of the DAC08 design is that supply current is

constant and independent of input logic states. This is useful in

cryptographic applications and further reduces the size of the

power supply bypass capacitors.

TEMPERATURE PERFORMANCE

The nonlinearity and monotonicity specifications of the DAC08

are guaranteed to apply over the entire rated operating tempera-

ture range. Full-scale output current drift is low, typically

±10 ppm/°C, with zero-scale output current and drift essentially

negligible compared to 1/2 LSB.

The temperature coefficient of the reference resistor R14 should

match and track that of the output resistor for minimum overall

full-scale drift. Settling times of the DAC08 decrease approxi-

mately 10% at –55°C. At +125°C, an increase of about 15% is

typical.

The reference amplifier must be compensated by using a

capacitor from Pin 16 to V−. For fixed reference operation, a

0.01 µF capacitor is recommended. For variable reference

applications, refer to the Reference Amplifier Compensation for

Multiplying Applications section.

MULTIPLYING OPERATION

The DAC08 provides excellent multiplying performance with

an extremely linear relationship between IFS and IREF over a

range of 4 µA to 4 mA. Monotonic operation is maintained over

a typical range of IREF from 100 µA to 4.0 mA.

SETTLING TIME

The DAC08 is capable of extremely fast settling times, typically

85 ns at IREF = 2.0 mA. Judicious circuit design and careful

board layout must be used to obtain full performance potential

during testing and application. The logic switch design enables

propagation delays of only 35 ns for each of the 8 bits. Settling

time to within 1/2 LSB of the LSB is therefore 35 ns, with each

progressively larger bit taking successively longer. The MSB

settles in 85 ns, thus determining the overall settling time of

85 ns. Settling to 6-bit accuracy requires about 65 ns to 70 ns.

The output capacitance of the DAC08, including the package, is

approximately 15 pF; therefore the output RC time constant

dominates settling time if RL > 500 Ω.

Settling time and propagation delay are relatively insensitive to

logic input amplitude and rise and fall times, due to the high

gain of the logic switches. Settling time also remains essentially

constant for IREF values. The principal advantage of higher IREF

values lies in the ability to attain a given output level with lower

load resistors, thus reducing the output RC time constant.

Measuring the settling time requires the ability to accurately

resolve ±4 µA; therefore a 1 kΩ load is needed to provide

adequate drive for most oscilloscopes. The settling time fixture

shown in Figure 33 uses a cascade design to permit driving a

1 kΩ load with less than 5 pF of parasitic capacitance at the

measurement node. At IREF values of less than 1.0 mA, excessive

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