AD9854ASVZ datasheet(39/52 Pages) AD

39 / 52 page

AD9854

Rev. E | Page 39 of 52

SDIO

SCLK

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

Figure 58. Serial Port Write Timing Clock Stall Low

SDIO

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

SCLK

INSTRUCTION CYCLE

DON'T CARE

SDO

DATA TRANSFER CYCLE

Figure 59. 3-Wire Serial Port Read Timing Clock Stall Low

SDIO

SCLK

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

Figure 60. Serial Port Write Timing Clock Stall High

SDIO

SCLK

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

Figure 61. 2-Wire Serial Port Read Timing Clock Stall High

CR [8] is the internal update active bit. When this bit is set to

Logic 1, the I/O UD CLK pin is an output and the AD9854

generates the I/O UD CLK signal. When this bit is set to Logic 0,

external I/O UD CLK functionality is performed and the I/O

UD CLK pin is configured as an input.

CR [7] is reserved. Write to 0.

CR [6] is the inverse sinc filter bypass bit. When this bit is set,

the data from the DDS block goes directly to the output shaped

keying logic, and the clock to the inverse sinc filter is stopped.

Default is clear with the filter enabled.

CR [5] is the shaped keying enable bit. When this bit is set, the

output ramping function is enabled and is performed in

accordance with the CR [4] bit requirements.

CR [4] is the internal/external output shaped keying control bit.

When this bit is set to Logic 1, the output shaped keying factor is

internally generated and applied to both the I and Q paths.

When this bit is cleared (default), the output shaped keying

function is externally controlled by the user, and the ouput

shaped keying factor is the value of the I and Q output shaped

keying factor register. The two registers that are the output

shaped keying factors also default low such that the output is off

at power-up until the device is programmed by the user.

CR [3:2] are reserved. Write to 0.

CR [1] is the serial port MSB-/LSB-first bit. Default is low,

MSB first.

CR [0] is the serial port SDO active bit. Default is low, inactive.

AD9854ASVZ Datasheet(PDF) 39 Page - Analog Devices

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