AD7679 datasheet(18/20 Pages) AD

18 / 20 page

REV. B

AD7676

–18–

AD7676*

MC68HC11*

SER/

PAR

IRQ

MISO/SDI

SCK

I/O PORT

BUSY

SDOUT

SCLK

CNVST

EXT/

INT

INVSCLK

DVDD

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 22. Interfacing the AD7676 to SPI Interface

ADSP-21065L in Master Serial Interface

As shown in Figure 23, the AD7676 can be interfaced to the

ADSP-21065L using the serial interface in Master Mode without

any glue logic required. This mode combines the advantages of

reducing the wire connections and the ability to read the data during

or after conversion maximum speed transfer (DIVSCLK[0:1]

both LOW).

The AD7676 is configured for the Internal Clock Mode (EXT/INT

LOW) and acts, therefore, as the master device. The convert

command can be generated by either an external low jitter oscil-

lator or, as shown, by a FLAG output of the ADSP-21065L or by

a frame output TFS of one serial port of the ADSP-21065L that

can be used like a timer. The Serial Port on the ADSP-21065L

is configured for external clock (IRFS = 0), rising edge active

(CKRE = 1), external late framed sync signals (IRFS = 0,

LAFS = 1, RFSR = 1), and active HIGH (LRFS = 0). The Serial

Port of the ADSP-21065L is configured by writing to its receive

control register (SRCTL)—see the ADSP-2106x SHARC User’s

Manual. Because the Serial Port within the ADSP-21065L will

be seeing a discontinuous clock, an initial word reading has to

be done after the ADSP-21065L has been reset to ensure that

the Serial Port is properly synchronized to this clock during each

following data read operation.

AD7676*

ADSP-21065L*

SHARC

SER/

PAR

RFS

RCLK

FLAG OR TFS

SYNC

SDOUT

SCLK

CNVST

RDC/SDIN

EXT/

INT

DVDD

*ADDITIONAL PINS OMITTED FOR CLARITY

INVSYNC

INVSCLK

Figure 23. Interfacing to the ADSP-21065L Using

the Serial Master Mode

APPLICATION HINTS

Layout

The AD7676 has very good immunity to noise on the power

supplies as can be seen in Figure 21. However, care should still

be taken with regard to grounding layout.

The printed circuit board that houses the AD7676 should be

designed so the analog and digital sections are separated and

confined to certain areas of the board. This facilitates the use of

ground planes that can be easily separated. Digital and analog

ground planes should be joined in only one place, preferably

underneath the AD7676, or, at least, as close as possible to the

AD7676. If the AD7676 is in a system where multiple devices

require analog to digital ground connections, the connection

should still be made at one point only, a star ground point

that should be established as close as possible to the AD7676.

It is recommended to avoid running digital lines under the device

as these will couple noise onto the die. The analog ground plane

should be allowed to run under the AD7676 to avoid noise

coupling. Fast switching signals like

CNVST or clocks should be

shielded with digital ground to avoid radiating noise to other sec-

tions of the board and should never run near analog signal paths.

Crossover of digital and analog signals should be avoided. Traces

on different but close layers of the board should run at right

angles to each other. This will reduce the effect of feedthrough

through the board.

The power supply lines to the AD7676 should use as large a

trace as possible to provide low impedance paths and reduce the

effect of glitches on the power supply lines. Good decoupling is

also important to lower the supply’s impedance presented to

the AD7676 and reduce the magnitude of the supply spikes.

Decoupling ceramic capacitors, typically 100 nF, should be

placed on each power supply’s pins, AVDD, DVDD, and OVDD,

close to and ideally right up against these pins and their corre-

sponding ground pins. Additionally, low ESR 10

µF capacitors

should be located in the vicinity of the ADC to further reduce

low frequency ripple.

The DVDD supply of the AD7676 can be either a separate

supply or come from the analog supply, AVDD, or from the

digital interface supply, OVDD. When the system digital supply

is noisy, or fast switching digital signals are present, it is recom-

mended if no separate supply is available, to connect the DVDD

digital supply to the analog supply AVDD through an RC filter as

shown in Figure 5 and to connect the system supply to the inter-

face digital supply OVDD and the remaining digital circuitry.

When DVDD is powered from the system supply, it is useful to

insert a bead to further reduce high frequency spikes.

The AD7676 has four different ground pins: REFGND, AGND,

DGND, and OGND. REFGND senses the reference voltage and

should be a low impedance return to the reference because it

carries pulsed currents. AGND is the ground to which most inter-

nal ADC analog signals are referenced. This ground must be

connected with the least resistance to the analog ground plane.

DGND must be tied to the analog or digital ground plane,

depending on the configuration. OGND is connected to the

digital system ground.

The layout of the decoupling of the reference voltage is important.

The decoupling capacitor should be close to the ADC and

connected with short and large traces to minimize parasitic

inductances.

Evaluating the AD7676 Performance

A recommended layout for the AD7676 is outlined in the

evaluation board for the AD7676. The evaluation board package

includes a fully assembled and tested evaluation board,

documentation, and software for controlling the board from a

PC via the Eval-Control BRD2.

AD7679 Datasheet(PDF) 18 Page - Analog Devices

AD7679 Datasheet(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Descarga

Enlace URL