LM92 datasheet(6/25 Pages) TI

6 / 25 page

LM92

SNIS110D – MARCH 2000 – REVISED MARCH 2013

www.ti.com

Digital DC Characteristics (continued)

Unless otherwise noted, these specifications apply for +VS= +2.7V to +5.5V for LM92CIM . Boldface limits apply for TA = TJ

= TMIN to TMAX; all other limits TA= TJ= +25 °C, unless otherwise noted.

Typical(1)

Limits(2)

Unit

Symbol

Parameter

Conditions

(Limit)

T_CRIT_A Output Saturation Voltage

I OUT = 4.0 mA

0.8

V (max)

(3)

T_CRIT_A Delay

Conversions

(max)

t OF

Output Fall Time

C L = 400 pF

250

ns (max)

I O = 3 mA

(3)

For best accuracy, minimize output loading. 10k pull-ups resistors should be sufficient. Higher sink currents can affect sensor accuracy

with internal heating. This can cause an error of 0.64 °C at full rated sink current and saturation voltage based on junction-to-ambient

thermal resistance.

Serial Bus Digital Switching Characteristics

Unless otherwise noted, these specifications apply for +VS= +2.7V to +5.5V for LM92CIM . Boldface limits apply for TA = TJ

= TMIN to TMAX; all other limits TA= TJ= +25 °C, unless otherwise noted. CL (load capacitance) on output lines = 80 pF unless

otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = +25 °C, unless otherwise noted.

Typical(1)

Limits(2) (3)

Unit

Symbol

Parameter

Conditions

(Limit)

t 1

SCL (Clock) Period

2.5

µs(min)

ms(max)

t 2

Data in Set-Up Time to SCL High

100

ns(min)

t 3

Data Out Stable after SCL Low

ns(min)

t 4

SDA Low Set-Up Time to SCL Low (Start Condition)

100

ns(min)

t 5

SDA High Hold Time after SCL High (Stop Condition)

100

ns(min)

tTIMEOUT

SDA and SCL Time Low for Reset of Serial Interface (4)

ms (min)

300

ms (max)

(1)

Typical values are at TA = 25 °C and represent most likely parametric norm.

(2)

Limits are guaranteed to TI's AOQL (Average Outgoing Quality Level).

(3)

Timing specifications are tested at the bus input logic levels (Vin(0)=0.3xVA for a falling edge and Vin(1)=0.7xVA for a rising edge) when

the SCL and SDA edge rates are similar.

(4)

Holding the SDA and/or SCL lines Low for a time interval greater than tTIMEOUT will cause the LM92 to reset SCL and SDA to the IDLE

state of the serial bus communication (SDA and SCL set High).

Figure 4. Serial Bus Communication

Submit Documentation Feedback

Product Folder Links: LM92

LM92 Datasheet(PDF) 6 Page - Texas Instruments

LM92 Datasheet(HTML) 6 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Datasheet Descarga

Enlace URL