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Advanced Linear Devices

ALD500AU/ALD500A/ALD500

The ALD500AU/ALD500A/ALD500 operates with differential

voltages within the input amplifier common-mode voltage

range. The amplifier common-mode range extends from 1.5V

below positive supply to 1.5V above negative supply. Within

this common-mode voltage range, common-mode rejection is

typically 95dB.

The integrator output also follows the common-mode voltage.

When large common-mode voltages with near full-scale

differential input voltages are applied, the input signal drives

the integrator output to near the supply rails where the

integrator output is near saturation. Under such conditions,

linearity of the converter may be adversely affected as the

integrator swing can be reduced. The integrator output must

not be allowed to saturate. Typically, the integrator output can

swing to within 0.9V of either supply rails without loss of

linearity.

Analog Ground

ground, a common-mode voltage exists at the inputs. This

common mode signal is rejected by the high common mode

set at a fixed known voltage (i.e., power supply ground). All

other ground connections should be connected to digital

ground in order to minimize noise at the inputs.

The reference voltage can be anywhere from 1V of the power

supply voltage rails of the converter. Roll-over error is caused

by the reference capacitor losing or gaining charge due to the

stray capacitance on its nodes. The difference in reference for

(+) or (-) input voltages will cause a roll-over error. This error

can be minimized by using a large reference capacitor in

comparison to the stray capacitance.

Phase Control Inputs (A, B)

The A and B logic inputs select the ALD500AU/ALD500A/

ALD500 operating phase. The A and B inputs are normally

driven by a microprocessor I/O port or external logic, using

CMOS logic levels. For logic control functions of A and B logic

inputs, see Table 1.

By monitoring the comparator output during the Input Signal

Integration Phase, which is a fixed signal integrate time

period, the input signal polarity can be determined by the

microcontroller controlling the conversion. The comparator

output is HIGH for positive signals and LOW for negative

signals during the Input Signal Integration Phase. The state of

the comparator should be checked by the microcontroller at

the end of the Input Signal Integration Phase, just before

transition to the Reference Voltage Deintegration Phase. For

very low level input signals noise may cause the comparator

output state to toggle between positive and negative states.

For the ALD500AU/ALD500A/ALD500, this noise has been

minimized to typically within one count.

At the start of the Reference Voltage Deintegration Phase,

comparator output is set to HIGH state. During the Reference

Voltage Deintegration Phase, the microcontroller must monitor

the comparator output to make a HIGH-to-LOW transition as

the integrator output ramp crosses zero relative to analog

ground.

This transition indicates that the conversion is

complete. The microcontroller then stops and records the

pulse count. The internal comparator delay is 1

µsec, typically.

The comparator output is undefined during the Auto Zero

Phase.

Figure 4. Comparator Output

ANALOG INPUT

INTEGRATE

REFERENCE

DEINTEGRATE

ZERO

CROSSING

COMPARATOR

OUTPUT

(COUT)

REFERENCE

DEINTEGRATE

ZERO

CROSSING

INTEGRATOR

OUTPUT

(VINT)

ANALOG INPUT

INTEGRATE

INTEGRATOR

OUTPUT

(VINT)

EXTERNAL INPUT

POLARITY DETECTION

COMPARATOR

OUTPUT

(COUT)

0V

EXTERNAL INPUT

POLARITY DETECTION