ADE7912 datasheet(43/44 Pages) AD

43 / 44 page

Data Sheet

ADE7912/ADE7913

Rev. 0| Page 43 of 44

Table 19. EMI_CTRL Register (Address 0xE)

Bit Location

Bit Name

Default Value

Description

SLOT0

Controls the PWM control block pulse during Slot 0 of the CLKIN/4 clock (see the

DC-to-DC Converter section for details).

SLOT1

Controls the PWM control block pulse during Slot 1 of the CLKIN/4 clock.

SLOT2

Controls the PWM control block pulse during Slot 2 of the CLKIN/4 clock.

SLOT3

Controls the PWM control block pulse during Slot 3 of the CLKIN/4 clock.

SLOT4

Controls the PWM control block pulse during Slot 4 of the CLKIN/4 clock.

SLOT5

Controls the PWM control block pulse during Slot 5 of the CLKIN/4 clock.

SLOT6

Controls the PWM control block pulse during Slot 6 of the CLKIN/4 clock.

SLOT7

Controls the PWM control block pulse during Slot 7 of the CLKIN/4 clock.

Table 20. STATUS1 Register (Address 0xF)

Bit Location

Bit Name

Default Value

Description

2:0

Version

The ADE7912/ADE7913 version number.

ADC_NA

If the ADC outputs are not accessed during one ADC output period, the ADC_NA bit is

set to 1. When the STATUS1 register is read, the bit is cleared to 0.

6:4

Reserved

Reserved. These bits do not represent any functionality.

Reserved

Reserved. Internal functionality is associated with this bit.

ADE7912 Datasheet(PDF) 43 Page - Analog Devices