PIC18F4680ISPSQTP datasheet(59/482 Pages) MICROCHIP

59 / 482 page

Preliminary

DS39625C-page 57

PIC18F2585/2680/4585/4680

B4EIDH(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B4SIDL(6)

2585 2680 4585 4680

xxxx x-xx

uuuu u-uu

B4SIDH(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B4CON(6)

2585 2680 4585 4680

0000 0000

uuuu uuuu

B3D7(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B3D6(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B3D5(6)

2585 2680 4585 4680

xxxx xxxx

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B3D4(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B3D3(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B3D2(6)

2585 2680 4585 4680

xxxx xxxx

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B3D1(6)

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xxxx xxxx

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B3D0(6)

2585 2680 4585 4680

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B3DLC(6)

2585 2680 4585 4680

-xxx xxxx

-uuu uuuu

B3EIDL(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B3EIDH(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B3SIDL(6)

2585 2680 4585 4680

xxxx x-xx

uuuu u-uu

B3SIDH(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B3CON(6)

2585 2680 4585 4680

0000 0000

uuuu uuuu

B2D7(6)

2585 2680 4585 4680

xxxx xxxx

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B2D6(6)

2585 2680 4585 4680

xxxx xxxx

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B2D5(6)

2585 2680 4585 4680

xxxx xxxx

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B2D4(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B2D3(6)

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xxxx xxxx

uuuu uuuu

B2D2(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B2D1(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B2D0(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B2DLC(6)

2585 2680 4585 4680

-xxx xxxx

-uuu uuuu

B2EIDL(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B2EIDH(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

B2SIDL(6)

2585 2680 4585 4680

xxxx x-xx

uuuu u-uu

B2SIDH(6)

2585 2680 4585 4680

xxxx xxxx

uuuu uuuu

TABLE 4-4:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Applicable Devices

Power-on Reset,

Brown-out Reset

MCLR Resets,

WDT Reset,

RESET

Instruction,

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1:

One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt

vector (0008h or 0018h).

When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the

hardware stack.

See Table 4-3 for Reset value for specific condition.

Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read ‘0’.

This register reads all ‘0’s until the ECAN™ technology is set up in Mode 1 or Mode 2.

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