AMD-K6 datasheet(13/346 Pages) AMD

13 / 346 page

List of Figures

xiii

20695H/0—March 1998

AMD-K6® Processor Data Sheet

Preliminary Information

Figure 72. SMM Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195

Figure 73. TAP State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213

Figure 74. Debug Register DR7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217

Figure 75. Debug Register DR6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 76. Debug Registers DR5 and DR4 . . . . . . . . . . . . . . . . . . . . . . . . . 218

Figure 77. Debug Registers DR3, DR2, DR1, and DR0. . . . . . . . . . . . . . . 219

Figure 78. Clock Control State Transitions . . . . . . . . . . . . . . . . . . . . . . . . 228

Figure 79. Suggested Component Placement . . . . . . . . . . . . . . . . . . . . . . 230

Figure 80. K6STD Pulldown V/I Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 81. K6STD Pullup V/I Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239

Figure 82. CLK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243

Figure 83. Diagrams Key . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 84. Output Valid Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254

Figure 85. Maximum Float Delay Timing . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 86. Input Setup and Hold Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 255

Figure 87. Reset and Configuration Timing . . . . . . . . . . . . . . . . . . . . . . . 256

Figure 88. TCK Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 89. TRST# Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 90. Test Signal Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 257

Figure 91. Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260

Figure 92. Power Consumption vs. Thermal Resistance . . . . . . . . . . . . . 260

Figure 93. Processor Heat Dissipation Path . . . . . . . . . . . . . . . . . . . . . . . 261

Figure 94. Measuring Case Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . 262

Figure 95. Voltage Regulator Placement . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 96. Airflow for a Heatsink with Fan . . . . . . . . . . . . . . . . . . . . . . . . 263

Figure 97. Airflow Path in a Dual-fan System . . . . . . . . . . . . . . . . . . . . . . 264

Figure 98. Airflow Path in an ATX Form-Factor System . . . . . . . . . . . . . 265

Figure 99. AMD-K6 Processor Top-Side View . . . . . . . . . . . . . . . . . . . . . . 267

Figure 100. AMD-K6 Processor Pin-Side View . . . . . . . . . . . . . . . . . . . . . . 268

Figure 101. 321-Pin Staggered CPGA Package Specification . . . . . . . . . . 272

Part Two

AMD-K6 Processor Model 7

275

Figure 102. Extended Feature Enable Register (EFER) . . . . . . . . . . . . . . 282

Figure 103. SYSCALL/SYSRET Target Address Register (STAR) . . . . . . 283

Figure 104. AMD-K6 Processor Model 7 Top-Side View. . . . . . . . . . . . . . . 315

Figure 105. AMD-K6 Processor Model 7 Pin-Side View . . . . . . . . . . . . . . . 316

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