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APU428 Datasheet(PDF) 5 Page - Aplus Intergrated Circuits |
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APU428 Datasheet(HTML) 5 Page - Aplus Intergrated Circuits |
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5 / 18 page ![]() Pad Name I/O Description IOB1~4 I/O I/O Input/Output port B. IOB1, 2 shares pins with SEG41, 42, or ELC, ELP and is set by mask option. IOB3, 4 shares pins with BZ, BZB and is set by mask option. IOC1~4 I/O I/O Input/Output port C can use software to define the internal pull-low/ low-level hold resistor and chattering clock in order to reduce input bounce and generate interrupt. This port shares pins with AN1-4 and is set by mask option. IOD1~4 I/O Input / Output port D. This port shares pins with SEG33~36 and is set by mask option. IOD3,4 shares pins with PWM1,2 and is set by mask option. RFC CC RR RT RH I O O O 1 input pin and 3 output pins for RFC application. This port shares pins with SEG37~40 and is set by mask option. This port shares pins with IOA1~4 and is set by mask option. EL ELC ELP O O Output port for the EL-light. These ports share pins with SEG41, 42 and are set by mask option. These ports share pins with IOB1, 2 and are set by mask option. ALM BZB Z O O Output port for alarm, frequency or melody generator. This port shares pins with IOB3,4 and is set by mask option. GND Negative supply voltage. Preliminary 5 Ver. 0.0 APU428 |
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