AS8501 - Data Sheet

austriamicrosystems

Revision 1.1, 04-April-06

www.austriamicrosystems.com

Page 16 of 40

7.5.1

OPM operation mode register ( 4 bits )

no.

Bit

mo3

mo2

mo1

mo0

Note

0

default

0

0

0

0

1)

1)

This register has been described in detail under 7.4

7.5.2

CRG general configuration register ( 28 bits )

no.

CRG bits

27-22

21-11

10-7

6-0

NOTE

0

CRS

CRI

CRV

CRP

subregister CRS: Sequence length, dechop and chop ( 6 bits )

Nr.

Bits

5

4

3

2

1

0

NOTE

0

CRS bit

names

s3

s2

s1

s0

d

1

Default

0

0

0

1

1

Notes:

1)

This register defines the sequence length, chopping (c) and dechopping (d) of the input signal

2)

Default power-up state before any setting

Sequence length bits ( 4bits)

Nr.

No. of measurements

s3

s2

s1

s0

NOTE

0

16

0

0

0

1

1

0

0

0

1 default

…

…

…

…

…

…

14

14

1

1

1

0

15

15

1

1

1

1

Notes:

1)

Number of consecutive measurements of A and B with settings defined in CRA,CRB

and other settings in CRG register. This setting is used only for mode MMD.

DECHOPPING BIT

Nr.

Dechopping

d

NOTE

0

No dechopping

0

1

Dechopping

1

CHOPPING BIT

Nr.

Chopping

c

NOTE

0

No chopping

0

1

chopping

1

subregister CRI: Current configuration ( 11 bits )

Nr.

Bits

10

9

8

7

6

5

4

3

2

1

0

NOTE

0

CRI bit

names

M14

M13

M12

M11

M8

M6

i4

i3

I2

i1

1

Default

0

0

0

0

0

0

0

0

0

0

2

output

VBAT

RSHL

RSHH

no

ETS

ETR

Notes:

1)

whenever M1=1 in (CRA,CRB) it is good practice to set all M6 to M14 to zero, but it is not mandatory

2)

default logic state after power up and before any setting

3)

All bits with names M14 to M1 represent control signals of the multiplexer with positive logic (for example M14=1

means that corresponding switch is closed).