LP38852 datasheet(13/29 Pages) TI

13 / 29 page

LP38852

www.ti.com

SNVS482E – JANUARY 2007 – REVISED APRIL 2013

Table 1 lists some suggested, best fit, standard ±1% resistor values for R1 and R2, and a standard ±10%

capacitor values for CFF, for a range of VOUT values. Other values of R1, R2, and CFF are available that will give

similar results.

Table 1.

VOUT

CFF

0.8V

1.07 k

Ω

1.78 k

Ω

12 nF

12.4 kHz

0.9V

1.50 k

Ω

1.87 k

Ω

8.2 nF

12.9 kHz

1.0V

1.00 k

Ω

1.00 k

Ω

12 nF

13.3 kHz

1.1V

1.65 k

Ω

1.37 k

Ω

8.2 nF

11.8 kHz

1.2V

1.40 k

Ω

1.00 k

Ω

10 nF

11.4 kHz

1.3V

1.15 k

Ω

715

Ω

12 nF

11.5 kHz

1.4V

1.07 k

Ω

590

Ω

12 nF

12.4 kHz

1.5V

2.00 k

Ω

1.00 k

Ω

6.8 nF

11.7 kHz

1.6V

1.65 k

Ω

750

Ω

8.2 nF

11.8 kHz

1.7V

2.55 k

Ω

1.07 k

Ω

5.6 nF

11.1 kHz

1.8V

2.94 k

Ω

1.13 k

Ω

4.7 nF

11.5 kHz

Please refer to Application Note 1378 for additional information on how resistor tolerances affect the calculated

VOUT value.

INPUT VOLTAGE

The input voltage (VIN) is the high current external voltage rail that will be regulated down to a lower voltage,

which is applied to the load. The input voltage must be at least VOUT + VDO, and no higher than whatever value is

used for VBIAS.

BIAS VOLTAGE

The bias voltage (VBIAS) is a low current external voltage rail required to bias the control circuitry and provide

gate drive for the N-FET pass transistor. When VOUT is set to 1.20V, or less, VBIAS may be anywhere in the

operating range of 3.0V to 5.5V. If VOUT is set higher than 1.20V, VBIAS must be between 4.5V and 5.5V to

ensure proper operation of the device.

UNDER VOLTAGE LOCKOUT

The bias voltage is monitored by a circuit which prevents the device from functioning when the bias voltage is

below the Under-Voltage Lock-Out (UVLO) threshold of approximately 2.45V.

As the bias voltage rises above the UVLO threshold the device control circuitry becomes active. There is

approximately 150 mV of hysteresis built into the UVLO threshold to provide noise immunity.

When the bias voltage is between the UVLO threshold and the Minimum Operating Rating value of 3.0V the

device will be functional, but the operating parameters will not be within the ensured limits.

SUPPLY SEQUENCING

There is no requirement for the order that VIN or VBIAS are applied or removed.

One practical limitation is that the Soft-Start circuit starts charging CSS when both VBIAS rises above the UVLO

threshold and the Enable pin is above the VEN(ON) threshold. If the application of VIN is delayed beyond this point

the benefits of Soft-Start will be compromised.

In any case, the output voltage cannot be specified until both VIN and VBIAS are within the range of specified

operating values.

If used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin

must be diode clamped to ground. A Schottky diode is recommended for this diode clamp.

Submit Documentation Feedback

Product Folder Links: LP38852

LP38852 Datasheet(PDF) 13 Page - Texas Instruments

LP38852 Datasheet(HTML) 13 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Datasheet Descarga

Enlace URL