PCM3003 datasheet(19/23 Pages) BURR-BROWN

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PCM3002/3003

IZD:

Bit 4

DAC Infinite Zero Detection Circuit

Control

This bit enables the Infinite Zero Detection Circuit

in PCM3002. When enabled, this circuit will dis-

connect the analog output amplifier from the delta-

sigma DAC when the input is continuously zero for

65,536 consecutive cycles of BCKIN.

IZD

Infinite Zero Detection Disabled (default)

Infinite Zero Detection Enabled

OUT:

Bit 3

DAC Output Enable Control

When set to “1”, the outputs are forced to VCC/2

(bipolar zero). In this case, all registers in

PCM3002 hold the present data. Therefore, when

set to “0”, the outputs return to the previous

programmed state.

OUT

DAC Outputs Enabled (default normal operation)

DAC Outputs Disabled (forced to BPZ)

DEM (1:0):Bit 2,1

DAC De-emphasis Control

These bits select the de-emphasis mode as shown

below:

DEM1

DEM0

De-emphasis 44.1kHz ON

De-emphasis OFF (default)

De-emphasis 48kHz ON

De-emphasis 32kHz ON

MUT:

Bit 0

DAC Soft Mute Control

When set to “1”, both left and right-channel DAC

outputs are muted at the same time. This muting

is done by attenuating the data in the digital filter,

so there is no audible click noise when soft mute

is turned on.

MUT

Mute Disable (default)

Mute Enable

PROGRAM REGISTER 3

A (1:0):

Bit 10:9

These bits define the address for REGISTER 3:

res:

Bit 15:11, 8:6, 4:0

Reserved

These bits are reserved, and should be set to “0”.

PROGRAM REGISTER 2

A (1:0):

Bit 10, 9

These bits define the address for REGISTER 2:

res:

Bit 15:11, 6 Reserved

These bits are reserved and should be set to “0”.

PDAD:

Bit 8

ADC Power-Down Control

This bit places the ADC section in the lowest

power consumption mode. The ADC operation is

stopped by cutting the supply current to the ADC

section, and DOUT is fixed to zero during ADC

Power-down mode enable. Figure 8 illustrates the

ADC DOUT response for ADC power-down ON/

OFF. This does not affect the DAC operation.

PDAD

DAC POWER-DOWN

Power Down Mode Disabled (default)

Power Down Mode Enabled

BYPS:

Bit 7

ADC High-Pass Filter Bypass Control

This bit enables or disables the high-pass filter for

the ADC.

BYPS

High-Pass Filter Enabled (default)

High-Pass Filter Disabled (bypassed)

PDDA:

Bit 6

DAC Power-Down Control

This bit places the DAC section in the lowest power

consumption mode. The DAC operation is stopped

by cutting the supply current to the DAC section

and VOUT is fixed to GND during DAC Power-

Down Mode enable. Figure 8 illustrates the DAC

VOUT response for DAC Power-Down ON/OFF.

This does not affect the ADC operation.

PDDA

Power-Down Mode Disabled (default)

Power-Down Mode Enabled

ATC:

Bit 5

DAC Attenuation Channel Control

When set to “1”, the REGISTER 0 attenuation

data can be used for both DAC channels. In this

case, the REGISTER 1 attenuation data is ig-

nored.

ATC

Individual Channel Attenuation Data Control (default)

Common Channel Attenuation Data Control

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