CAT28C17API-20T datasheet(6/8 Pages) CATALYST

No. de pieza	CAT28C17API-20T

Descripción Electrónicos	16K-Bit CMOS PARALLEL E2PROM

PDF	8 Pages

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Fabricante Electrónico	CATALYST [Catalyst Semiconductor]

Página de inicio	http://www.catalyst-semiconductor.com

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6 / 8 page

CAT28C17A

Doc. No. 25034-00 2/98

ADDRESS

tRC

DATA OUT

DATA VALID

tCE

tOE

tOH

tAA

tOHZ

tHZ

VIH

HIGH-Z

tLZ

tOLZ

DEVICE OPERATION

Read

Data stored in the CAT28C17A is transferred to the data

bus when WE is held high, and both OE and CE are held

low. The data bus is set to a high impedance state when

either CE or OE goes high. This 2-line control architec-

ture can be used to eliminate bus contention in a system

environment.

28C17A F05

Figure 4. Byte Write Cycle [WE Controlled]

ADDRESS

tAS

DATA IN

DATA VALID

tCS

tAH

tCH

tWC

tOEH

tDL

tDH

tDS

tOES

tWP

RDY/BUSY

tDB

DATA OUT

HIGH-Z

5091 FHD F06

Ready/BUSY (RDY/BUSY)

The RDY/BUSY pin is an open drain output which

indicates device status during programming. It is pulled

low during the write cycle and released at the end of

programming. Several devices may be OR-tied to the

same RDY/BUSY line.

Figure 3. Read Cycle

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