ES1010SI datasheet(9/11 Pages) ALTERA

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Page 9

ES1010SI 12V Hot-Swap Power Distribution Controllers

March 2014 Altera Corporation

EVB-ES1010SI Board

The EVB-ES1010SI is default provided as a +12V high side switch controller with the CR level set at ~2.5A. See Figure 11 for

EVB-ES1010SI schematic and Table 3 for BOM. Bias and load connection points are provided along with test points for each IC

pin.

With J1 installed the ES1010SI will be biased from the +12V supply (VIN) being switched. Connect the load to VLOAD+. EN pin

pulls high internally enabling the ES1010SI if not driven low via EN test point or J2.

With R3 = 1.24k the CR Vth is set to 24.8mV and with the 10m sense resistor (R1) the EVB-ES1010SI has a nominal CR level

of 2.5~A. The 0.01µF delay time to latch-off capacitor results in a nominal 1ms before latch-off of output after an OC event.

Reconfiguring the EVB-ES1010SI board for a higher CR level can be done by changing the RSENSE and/or RISET- resistor values as

the provided FET is rated for a much higher current.

FIGURE 12. IOC REGULATION and TURN-OFF

FIGURE 13. WOC TURN-OFF and RESTART

FIGURE 14. EVB-ES1010SI HIGH SIDE SWITCH APPLICATION

Typical Performance Curves (Continued)

VOUT

GATE

ILOAD

CLTIM

VOUT

GATE

ILOAD

CLTIM

ES1010SI

VBIAS

VIN

+12V

VBIAS

AGND

VLOAD+

VOUT

CCLTIM

POK

09617

March 14, 2014

Rev A

ES1010SI Datasheet(PDF) 9 Page - Altera Corporation