DAC10

REV. D

–7–

Figure 15. Positive Low Impedance Output Operation

Figure 16. Negative Low Impedance Output Operation

Figure 17. Interfacing with Various Logic Families

Figure 14. Settling Time Measurement

DAC10

OP01

4

2

FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE

LOGIC DAC), CONNECT INVERTING INPUT OF OP AMP TO

1023

1024

2

DAC10

OP15

4

2

1023

1024

2

FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE

LOGIC DAC), CONNECT NOINVERTING INPUT OF OP AMP TO

ECL

13k

–5.2V

TO PIN 1

2N3904

"A"

39k

3k

6.2k

2N3904

+15V

9.1k

+15V CMOS

6.2k

0.1 F

DAC10

TTL

1

51

2.5k

2.5k

10k

1M

1/4W, 5%

CARBON

2k

4k

1k

499k

1/4W, 5% CARBON

0.01 F

1 F

0.01 F

0.1 F10 F

4.7 F

0.01 F

1 F

0.01 F

4.7 F

0.1 F10 F

+15V

0.500V

0.001V

+15V

–15V

–15V

+15V

15 16 18

3

17 1

2

5

14

4

2

6

5

4

REF-01

–15V

–15V

175mV

2N918

2N918

1/2 LSB SETTLING = 7.8mV

NOTES:

1. CASE OF 2N918s MUST BE GROUNDED.

2. RESISTORS ARE 1/4W MF, 1% UNLESS OTHERWISE SPECIFIED.

3. USE FET PROBE (7A11 SCOPE PLUGIN).

D.U.T.

IN5711