ICS672-01/02

QuadraClock™ Quadrature Delay Buffer

MDS 672-01/02 C

3

Revision 112200

Integrated Circuit Systems, Inc.• 525 Race Street • San Jose •CA•95126• (408) 295-9800 tel • www.icst.com

Operation and Applications

The ICS672-01/02 each provide a total of five output clocks with multiple phase shifts relative to the input

clock (ICLK). Phase shifts of 0° (CLK0), 90° (CLK90), 180° (CLK180), and 270° (CLK270) are provided,

plus one feedback clock (FBCLK). All output clocks will be a multiple of the input clock, as determined by

the table on page 2.

Refer to the illustrations in Figure 1 and Figure 2.

FBCLK is connected to the feedback input (FBIN) to provide a zero delay through the ICS672-01/02.

FBCLK has a 0° phase shift from ICLK.

Figure 1. Phase alignment of input and output clocks. (x1 multiplier)

CLK90

CLK180

CLK0,

FBCLK

CLK270

ICLK

Figure 2. Phase alignment of input and output clocks. (x2 multiplier)

CLK90

CLK180

CLK0,

FBCLK

CLK270

ICLK