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ICS9159-12 Datasheet(PDF) 1 Page - Integrated Circuit Systems |
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ICS9159-12 Datasheet(HTML) 1 Page - Integrated Circuit Systems |
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1 / 5 page ![]() Integrated Circuit Systems, Inc. General Description Features ICS9159-12 Frequency Generator and Buffers for Mobile Pentium Systems 9159-12RevB071797 Block Diagram The ICS9159-12 generates all clocks required for mobile microprocessor systems based on Pentium/Mobile Triton chip sets. Three different reference frequency multiplying factors are externally selectable with smooth frequency transitions. These multiplying factors can be customized for specific plications. A test mode is provided to drive all clocks directly. High drive BCLK outputs provide greater than 1V/ns slew rate into 30pF loads. PCLK outputs provide better than 1V/ ns slew rate into 20pF loads while maintaining ±5% duty cycle. Generates 14 clocks including processor, disk and reference Meets all Pentium/Mobile Triton 82430MX requirments Independent buffers provide 4 and 6 clock copies Buffered clocks skew matched to ±250ps Buffer inputs are 5V tolerant Test clock mode eases system design Selectable multiplying and processor/bus ratios Custom configurations available 3.0V- 5.5V supply range 28pin, .209" SSOP package Pentium is a trademark of Intel Corporation. FS1 FS0 *VCO X1, REF (MHz) CPU (MHz) 0 0 118/17*X1 14.318 50 (49.69) 0 1 65/7*X1 14.318 66.6 (66.47) 1 0 92/11*X1 14.318 60 (59.87) 1 1 Test mode TCLK TCLK/2 CPU 24M VCO/2 24 MHz TCLK/2 TCLK/4 Functionality *VCO range is limited form 60 - 200 MHz. Pin Configuration 28-Pin SSOP ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. |
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