5

ICS9248-126

Third party brands and names are the property of their respective owners.

Byte 1: CPU, Active/Inactive Register

(1= enable, 0 = disable)

Byte 2: PCI, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

)

#

3

.

3

_

5

.

2

U

P

C

(

6

t

i

B4

11

)

t

c

a

n

I

/

t

c

A

(

6

K

L

C

I

C

P

5

t

i

B3

11

)

t

c

a

n

I

/

t

c

A

(

5

K

L

C

I

C

P

4

t

i

B2

11

)

t

c

a

n

I

/

t

c

A

(

4

K

L

C

I

C

P

3

t

i

B1

11

)

t

c

a

n

I

/

t

c

A

(

3

K

L

C

I

C

P

2

t

i

B9

1

)

t

c

a

n

I

/

t

c

A

(

2

K

L

C

I

C

P

1

t

i

B8

1

)

t

c

a

n

I

/

t

c

A

(

1

K

L

C

I

C

P

0

t

i

B7

1

)

t

c

a

n

I

/

t

c

A

(

0

K

L

C

I

C

P

Notes:

1. Inactive means outputs are held LOW and are disabled

from switching.

2. Latched Frequency Selects (FS#) will be inferted logic

load of the input frequency select pin conditions.

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B5

21

z

H

M

8

4

_

4

2

6

t

i

B6

21

z

H

M

8

4

5

t

i

B1

41

3

1

M

A

R

D

S

4

t

i

B0

41

2

1

M

A

R

D

S

3

t

i

B8

31

1

1

M

A

R

D

S

2

t

i

B7

31

0

1

M

A

R

D

S

1

t

i

B5

31

9

M

A

R

D

S

0

t

i

B4

31

8

M

A

R

D

S

Byte 4: Reserved , Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

d

e

v

r

e

s

e

R

6

t

i

B-

1

d

e

v

r

e

s

e

R

5

t

i

B-

1

#

3

S

F

4

t

i

B-

1

#

2

S

F

3

t

i

B-

1

#

1

S

F

2

t

i

B-

1

#

0

S

F

1

t

i

B8

41

)

t

c

a

n

I

/

t

c

A

(

1

F

E

R

0

t

i

B2

1

)

t

c

a

n

I

/

t

c

A

(

0

F

E

R

Byte 5: Peripheral , Active/Inactive Register

(1= enable, 0 = disable)

Byte 3: SDRAM, Active/Inactive Register

(1= enable, 0 = disable)

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B2

31

)

t

c

a

n

I

/

t

c

A

(

7

M

A

R

D

S

6

t

i

B1

31

)

t

c

a

n

I

/

t

c

A

(

6

M

A

R

D

S

5

t

i

B9

21

)

t

c

a

n

I

/

t

c

A

(

5

M

A

R

D

S

4

t

i

B8

21

)

t

c

a

n

I

/

t

c

A

(

4

M

A

R

D

S

3

t

i

B1

21

)

t

c

a

n

I

/

t

c

A

(

3

M

A

R

D

S

2

t

i

B0

21

)

t

c

a

n

I

/

t

c

A

(

2

M

A

R

D

S

1

t

i

B8

11

)

t

c

a

n

I

/

t

c

A

(

1

M

A

R

D

S

0

t

i

B7

11

)

t

c

a

n

I

/

t

c

A

(

0

M

A

R

D

S

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

1

#

8

4

_

4

2

L

E

S

)

0

o

t

t

e

s

n

e

h

w

z

H

M

8

4

(

)

1

o

t

t

e

s

n

e

h

w

z

H

M

4

2

(

6

t

i

B-

1

d

e

v

r

e

s

e

R

5

t

i

B-

1

d

e

v

r

e

s

e

R

4

t

i

B-

1

d

e

v

r

e

s

e

R

3

t

i

B3

41

)

t

c

a

n

I

/

t

c

A

(

2

K

L

C

U

P

C

2

t

i

B5

41

)

t

c

a

n

I

/

t

c

A

(

1

K

L

C

U

P

C

1

t

i

B6

41

)

t

c

a

n

I

/

t

c

A

(

0

K

L

C

U

P

C

0

t

i

B-

1

d

e

v

r

e

s

e

R

T

I

B#

N

I

PD

W

PN

O

I

T

P

I

R

C

S

E

D

7

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

6

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

5

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

4

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

3

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

2

t

i

B-

1

)

e

t

o

N

(

d

e

v

r

e

s

e

R

1

t

i

B-

1

)

e

t

o

N

(

d

e

v

r

e

s

e

R

0

t

i

B-

0

)

e

t

o

N

(

d

e

v

r

e

s

e

R

Byte 6: Peripheral , Active/Inactive Register

(1= enable, 0 = disable)

Note: Don’t write into this register, writing into this

register can cause malfunction