MK74CB163

1 to 16 PECL to CMOS Buffalo™ Clock Driver

MDS 74CB163 A

3

Revision 112399

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408)295-9800tel • www.icst.com

PRELIMINARY INFORMATION

Electrical Specifications

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (Note 1)

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage, VDD

Referenced to GND

7

V

Inputs

Referenced to GND

0.5

VDD+0.5

V

Clock Outputs

Referenced to GND

0.5

VDD+0.5

V

Ambient Operating Temperature

0

70

°C

Soldering Temperature

Max of 20 seconds

260

°C

Storage Temperature

-65

150

°C

DC CHARACTERISTICS (VDD = 3.3 V unless noted)

DC CHARACTERISTICS (VDD = 3.3 V unless noted)

Operating Voltage, VDD

3.0

3.6

V

Input High Voltage, VIH (OE0, OE1 pins)

2.0

V

Input Low Voltage, VIL (OE0, OE1 pins)

0.8

V

Output High Voltage, VOH

IOH=-12mA

VDD-0.5

V

Output Low Voltage, VOL

IOL=12mA

0.5

V

Operating Supply Current, IDD, at 66.6MHz

No Load

TBD

mA

Short Circuit Current

Each output

±70

mA

On-Chip Pull-up Resistor

OE0, OE1

250

k

Ω

Input Capacitance (OE0, OE1)

7

pF

Peak-to-Peak Input Voltage, VPP

PECL inputs

300

1000

mV

Common Mode Range, VCMR

PECL inputs

VDD-1.4

VDD-0.6

V

AC CHARACTERISTICS (VDD = 3.3 V unless noted)

AC CHARACTERISTICS (VDD = 3.3 V unless noted)

Input Clock Frequency

0

156

MHz

Propagation Delay with load=15pF

ns

Output Clock Rise Time

0.8 to 2.0V

ns

Output Clock Fall Time

2.0 to 0.8V

ns

Output Clock Rising Edge Skew

Note 2

-250

0

250

ps

Output Enable Time, OE high to output on

5

20

ns

Output Disable Time, OE low to tri-state

5

20

ns

Output Duty Cycle, Load = 15 pF at VDD/2

0-125 MHz

45

50

55

%

Output Duty Cycle, Load = 15 pF at VDD/2

125-156 MHz

40

50

60

%

Notes:

1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure to levels

above the operating limits but below the Absolute Maximums may affect device reliability.

2. Between any two outputs, with equal loading, measured at VDD/2. The maximum skew between any 2 pins is 250 ps not 500 ps.