8X930AX datasheet(34/38 Pages) INTEL

34 / 38 page

ADVANCE INFORMATION

8x930Ax UNIVERSAL SERIAL BUS (USB) MICROCONTROLLER

6.0

THERMAL CHARACTERISTICS

This microcontroller operates over the commercial

temperature range from 0oC to 70oC. All thermal

impedance data (Table 16) is approximate for static

air conditions at 1 watt of power dissipation. Values

change depending on operating conditions and

application

requirements.

The

Intel

Packaging

Handbook (order number 240800) describes Intel’s

thermal

impedance

test

methodology.

The

Components Quality and Reliability Handbook

(order

number

210997)

provides

quality

and

reliability information.

7.0

PRODUCT REFERENCE

This section lists design considerations for the

8x930Ax Universal Serial Bus microcontroller.

7.1

External Bus Timing and

Peripheral Timing Affected by

PLLSEL2:0 Selection

PLLSEL2 (pin43), PLLSEL1 (pin 42), and PLLSEL0

(pin 44) determine the 8

x930Ax internal CPU

operating frequency. The selected CPU operating

frequency also influences all the peripherals. If the

PLLSEL2:0 pins of the 8

x930Ax are set to 110, then

the internal clock frequency is 12MHz, and one

state time equals one clock time (please refer to

Table 8 on page 12). Therefore, all internal and

external instruction times for the timer, serial port,

PCA,

are

two

times

faster

than

with

other

PLLSEL2:0 selections. Refer to the

8x930Ax,

8x930Hx

Universal

Serial

Bus

Microcontroller

User’s Manual for the new peripheral timing

formulas.

7.2

Low Clock Mode Frequency

In low clock mode, the CPU and peripherals run at 3

MHz. All external bus accesses are affected,

including instruction fetch, data read/write, and

peripheral timing. Please refer to Table 8 on page

12 for the relationship of 3 MHz CPU and peripheral

timing (T

CLK) to state times. One peripheral cycle is

6 state times.

7.3

Setting FFRC Bit Clears Only the

Oldest Packet in the FIFO

If the receive FIFO is set as a dual packet mode, it

can receive two packets. Setting FFRC to indicate

FIFO Read Complete will not flush the entire FIFO,

only the oldest packet will be flushed. The read

marker will be advanced to the location of the read

pointer.

7.4

Series Resistor Requirement for

Impedance Matching

Per the USB 1.0 specification (page 111, section

7.1.1.1), the impedance of the differential driver

must be between 29 and 44 Ohms. To match the

cable impedance, a series resistor of 27 to 33 Ohms

should be connected to each USB line; i.e., on D

(pin 55) and on D

0 (pin 54). If the USB line is

improperly terminated or not matched, signal fidelity

will suffer. This can be seen on the scope as

excessive overshoot and undershoot. This will

potentially introduce bit errors.

7.5

Pullup Requirement for Full

Speed Device and Low Speed

Device

The pullup is a USB requirement to allow the host to

identify which devices are low speed and which are

full speed in order to communicate at the appro-

priate data rate. For Full Speed devices (12 Mbps)

use a 1.5K pullup resistor (to 3.0 V – 3.6 V) on the

0 line. For Low Speed devices (1.5Mbps), use a

1.5K pullup resistor (to 3.0 V – 3.6 V) on the D

line.

7.6

Powerdown Mode Cannot Be

Invoked Before USB Suspend

If the 8

x930Ax is put into powerdown mode prior to

receiving a USB Suspend signal from the host, a

USB Resume will not properly wake up the

x930Ax from powerdown mode.

Table 16. Thermal Characteristics

Package Type

68-pin PLCC

N/A

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