LXT970ATC datasheet(13/74 Pages) INTEL

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Dual-Speed Fast Ethernet Transceiver — LXT970A

Datasheet

Table 4.

LXT970A Twisted-Pair Interface Signal Descriptions

Pin#1

Pin Name

I/O2

Signal Description

TPOP

TPON

Twisted-Pair Output, Positive and Negative. Differential driver pair produces 802.3-

compliant pulses for either 100BASE-TX or 10BASE-T transmission.

TREF

Transmit Reference. Tie to center tap of output transformer.

TPIP

TPIN

Twisted-Pair Input, Positive and Negative. Differential input pair for either 100BASE-TX

or 10BASE-T reception.

1. Pin numbers apply to all package types.

2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog

Table 5.

LXT970A LED Indicator Signal Descriptions

Pin#1

Pin Name

I/O2

Signal Description3

LEDS

Speed LED. Active Low output indicates 100 Mbps operation is selected.

LEDR

Receive LED. Active Low output indicates that receiver is active.

LEDT

Transmit LED. Active Low output indicates transmitter is active.

LEDL

Link LED. Active Low output;

During 100 Mbps operation, indicates scrambler lock and receipt of valid Idle codes.

During 10 Mbps operation, indicates Link Valid status.

LEDC

Collision LED. In default mode, active Low output indicates collision. However, LEDC is

programmable and may be set for other indications. For programming options, see

Configuration Register 19 in Table 55, “Configuration Register (Address 19, Hex 13)” on

page 71.

1. Pin numbers apply to all package types.

2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.

3. LEDs are read at power-up to determine scrambler seed values.

Table 6.

LXT970A Miscellaneous Signal Descriptions

Pin#1

Pin Name

I/O2

Signal Description

TEST

Test. Must be tied Low.

Crystal Input and Output. Use a clock at XI or connect a 25 MHz crystal oscillator across

XI and XO. Refer to the Functional Description section for detailed clock requirements on

page 18.

RBIAS

Bias Control. Controls operating circuit bias via an external 22.1 k

Ω, 1% resistor to

ground.

RESET

Reset. This active Low input is OR’ed with the control register Reset bit (0.15). The

LXT970A reset cycle is extended 300

µs (nominal) after Reset is de-asserted.

PWRDWN

Power Down. When High, forces LXT970A into power down mode. This pin is OR’ed with

the Power Down bit (0.11). Refer to Table 45 for more information.

32, 35,

N/C

No Connection. Leave open.

1. Pin numbers apply to all package types.

2. I/O Column Coding: I = Input, O = Output, OD = Open Drain, A = Analog.

LXT970ATC Datasheet(PDF) 13 Page - Intel Corporation

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