4-67

CDP1871A, CDP1871AC

FIGURE 1. TYPICAL CDP1800 SERIES MICROPROCESSOR SYSTEM USING THE CDP1871A

FIGURE 2. CDP1871A BLOCK DIAGRAM

0.1

µF

36

100K

40

DEBOUNCE

CS1,

CS2,

CS3

CS4

TPB

SHIFT

23

24

21

34

CONTROL

ALPHA

39

CONTROL

SHIFT

38

BUS0-BUS7

CONTROL

MRD

D11

D1

ALPHA LOCK

NORMAL

TPB

N0-N2

37

BUS0-BUS7

CDP1800-SERIES

CPU

CDP1871A

S1

12

S2

13

S3

14

S4

15

S5

16

S6

17

S7

18

S8

19

8 BIT DATA BUS

11

UP TO 11 SETS

OF 8 SWITCHES EACH

1

32

25

CS1

CS2

CS3

21

22

23

24

34

CS4

TPB

CS

CONTROL

LOGIC

KEY

DETECT

36

DEBOUNCE

F/F

33

DA

35

RPT

STATUS

LATCHES

KEY DOWN

DETECT

1 OF 8

MUX

FROM

KEY BOARD

12

19

SENSE

LINES

1

11

TO

KEY BOARD

DRIVE

LINES

DI

DII

37

ALPHA

DECODER/

DRIVERS

II

LATCH

39

SHIFT

38

CONTROL

THREE-STAGE

SCAN COUNTER

FIVE-STAGE

SCAN COUNTER

C1-C3

C4-C8

THREE-STATE

OUTPUT

BUFFERS

BUS ENABLE

25

32

BUS 0

BUS 7

40

20

SCAN CLOCK