7-69

Pinout

28 LEAD SOIC

TOP VIEW

MCLK

TXCLK

TX_EN

TX_DATA

RESET

DGND

AVCC

AGND

IBBOUT

QBBOUT

QBBIN

IBBIN

DAC_REF

VCM_REF

CCLK

C_EN

DVCC

RCLK

AGND

VCO_IN

AVCC

MOD_OUT-

MOD_OUT+

AVDD

AGND

CDATA

PD_OUT

VCO_SET

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

Pin Description

SYMBOL

TYPE

DESCRIPTION

MCLK

I

Master clock input (25.6MHz). (D)

TXCLK

O

PSK data clock (256kHz) for PSK_DATA_IN. (D)

TX_EN

I

Transmit Enable. When high, the modulator output is enabled. This pin should be high for the entire burst. The signal is

extended internally until data has fully exited the part before turning off for spurious free turn on and turn off. (D)

TX_DATA

I

256 KBPS serial data input. (D)

RESET

I

Digital Reset Pin (active low). The part is reset immediately on assertion of the reset pin. The output of the part is

disabled on the assertion of reset. The part will come out of reset 2 master clock periods after the reset is de-

asserted. Reprogramming (see Control Interface Section) is needed after deassertion of reset for proper opera-

tion. (D)

DGND

I

Negative supply for the digital filters and control. (P)

AVCC

I

Positive supply for the quadrature modulator. AVCC should be tied to +5V analog. (P)

AGND

I

Negative supply for the quadrature modulator. AGND is tied to GND. (P)

IBBOUT

O

I baseband filtered output. (A)

QBBOUT

O

Q baseband filtered output. (A)

QBBIN

I

Q baseband modulator input. (A)

IBBIN

I

I baseband modulator input. (A)

DAC_REF

O

D/A reference node. A 0.1

µF capacitor to ground is suggested. (A)

VCM_REF

O

Modulator common mode reference node. A 0.1

µF capacitor to ground is suggested. (A)

AGND

I

Negative supply for the cable interface. (P)

AVDD

I

Positive supply for the cable interface (+9V analog). (P)

MOD_OUT+

O

Positive output drive pin for the cable interface. (A)

MOD_OUT-

O

Negative output drive pin for the cable interface. (A)

HSP50307