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UPD16337 Datasheet(PDF) 3 Page - NEC |
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UPD16337 Datasheet(HTML) 3 Page - NEC |
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3 / 16 page ![]() µPD16337 3 PIN CONFIGURATION (Top View) 100 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC VDD2 NC VSS2 NC O22 O21 O20 O19 O18 O17 O16 O15 O14 O13 O12 O11 O10 O9 O8 O7 O6 O5 O4 O3 O2 O1 NC VDD2 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 NC VDD2 NC VSS2 NC O43 O44 O45 O46 O47 O48 O49 O50 O51 O52 O53 O54 O55 O56 O57 O58 O59 O60 O61 O62 O63 O64 NC VDD2 NC 31 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 100-pin plaxtic QFP Cautions 1. Pin 40 is connected to the lead frame, and therefore must be left open. 2. Ensure that the VDD1, VDD2, VSS1 and VSS2 pins are all used, and that VSS1 and VSS2 are used at the same potential. 3. To prevent latch up breakdown, the power should be turned on in the order VDD1, logic signal, VDD2. It should be turned off in the opposite order. |
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