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UPD17709GC Datasheet(PDF) 3 Page - NEC |
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UPD17709GC Datasheet(HTML) 3 Page - NEC |
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3 / 356 page ![]() 3 µPD17704, 17705, 17707, 17708, 17709 Part Number µPD17704 µPD17705 µPD17707 µPD17708 µPD17709 Item Frequency counter • Intermediate frequency (IF) measurement P1C0/FMIFC pin : in FMIF mode 10 to 11 MHz in AMIF mode 0.4 to 0.5 MHz P1C1/AMIFC pin: in AMIF mode 0.4 to 0.5 MHz • External gate width measurement P2A1/FCG1, P2A0/FCG0 pin BEEP output 2 pins Output frequency: 1 kHz, 3 kHz, 4 kHz, 6.7 kHz (BEEP0 pin) 67 Hz, 200 Hz, 3 kHz, 4 kHz (BEEP1 pin) Reset • Power-ON reset (on power application) • Reset by RESET pin • Watchdog timer reset Can be set only once on power application: 65536 instruction, 131072 instruction, or no-use selectable • Stack pointer overflow/underflow reset Can be set only once on power application: interrupt stack or address stack selectable • CE reset (CE pin low → high level) CE reset delay timing can be set. • Power failure detection function Standby • Clock stop mode (STOP) • Halt mode (HALT) Supply voltage • PLL operation: VDD = 4.5 to 5.5 V • CPU operation: VDD = 3.5 to 5.5 V Package 80-pin plastic QFP (14 × 14 mm, 0.65 mm pitch) |
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