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GUIDELINES FOR UPGRADING FROM THE ST92F120 (0.50 µm) TO THE ST92F124...

2.5.2 PWM Mode

A Timer Interrupt can now be generated each time Counter = OC2R:

– To enable it, set OCIE or OC2IE,

– To disable it, reset OCIE AND OC2IE.

2.6 10-BIT ADC

Since the new ADC is entirely different, the program will have to be updated:

– All data registers are 10 bits, which includes the threshold registers. So each register is di-

vided into two 8-bit registers: an upper register and a lower register, in which only the 2 most

significant bits are used:

– The start conversion channel is now defined by bits CLR1[7:4] (Pg63, R252).

– The analog watchdog channels are selected by bits CLR1[3:0]. The only condition is that the

two channels must be contiguous.

– The ADC clock is selected with CLR2[7:5] (Pg63, R253).

– Interrupt registers have not been modified.

Because of the increased length of ADC registers, the register map is different. The location of

the new registers is given in the description of the ADC in the updated ST92F124/F150/F250

Datasheet.

2.7 I²C

2.7.1 IERRP BIT RESET

In the ST92F124/F150/F250 interrupt routine dedicated to the Error Pending event (IERRP is

set), a software loop must be implemented.

This loop checks every flag and executes the corresponding needed actions. The loop will not

end until all flags are reset.

At the end of this software loop execution, the IERRP bit is reset by software and the code

exits from the interrupt routine.

Table 7. DiHR

70

Di.9

Di.8

Di.7

Di.6

Di.5

Di.4

Di.3

Di.2

Table 8. DiLR

70

Di.1

Di.0

00

00

00