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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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ST9 Datasheet(PDF) 78 Page - STMicroelectronics |
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ST9 Datasheet(HTML) 78 Page - STMicroelectronics |
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78 / 146 page  78/146 ST9 USER GUIDE Figure 36 . MFT Interrupt Vector Register The Interrupt and DMA Mask Register individually enable and disable the various interrupt and DMA sources. Figure 37 . MFT Interrupt and DMA Mask Register The upper five bits of the Interrupt and DMA Control Register indicate the status of the inter- rupts and the DMA blocks. The lower three bits set the Interrupt and DMA priority level. 0 7 0 0 0 1 1 0 1 1 IVR (R242 page 9 MFT0) (R246 page 9 MFT1) Interrupt Vector Register Not used MSB of the vector by software inside the interrupt vector table address table, fixed LSB of the vector address table, fixed by hardware Overflow/underflow event interrupts Not Available Capture event interrupts Compare event interrupts Interrupt Source V4 V3 V2 V1 V0 W1 W0 D0 0 7 IDMR (R255) Interrupt / DMA Mask Register OVF Interrupt Mask Compare 1 Interrupt Mask Compare 0 Interrupt Mask Compare 0 DMA Mask Capture 1 Interrupt Mask Capture 0 Interrupt Mask Capture 0 DMA Mask Global Timer Interrupt Enable GTIEN CP0D CP0I CP1I CM0D CM0I CM1I 0UI |
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