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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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Motor de Búsqueda de Datasheet de Componentes Electrónicos |
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RM0312 Datasheet(PDF) 64 Page - STMicroelectronics |
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RM0312 Datasheet(HTML) 64 Page - STMicroelectronics |
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64 / 275 page  Clock control (CLK) RM0312 64/275 DocID022352 Rev 3 8.4.2 Peripheral clock gating register 1 (CLK_PCKENR1) Address offset: 0x03 Reset value: 0x00 8.4.3 Peripheral clock gating register 2 (CLK_PCKENR2) Address offset: 0x04 Reset value: 0x01 7 654 3210 PCKENR1[7:0] rw Bits 7:0 PCKENR1[7:0]: Peripheral clock enable 0: fMASTER to peripheral disabled 1: fMASTER to peripheral enabled These bits are written by software to enable or disable the fMASTER clock to the corresponding peripheral. See Table 15 Table 15. Peripheral clock gating bits Control bit Peripheral PCKENR17 ProxSense PCKENR16 AWU (except LSI clock controlled by AWUEN bit in the Control/status register (AWU_CSR)). PCKENR15 USART PCKENR14 SPI PCKENR13 I2C PCKENR12 TIM4 PCKENR11 TIM3 PCKENR10 TIM2 7 654 3210 Reserved PCKENR20 rw Bits 7:1 Reserved Bit 0 PCKENR20: WWDG peripheral clock enable 0: fMASTER to peripheral disabled 1: fMASTER to peripheral enabled (reset value) |
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