PM0223 datasheet(23/110 Pages) STMICROELECTRONICS

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PM0223

The STM32L0 Cortex-M0+ Processor

2.2.4

Additional memory access constraints for caches and shared memory

When a system includes caches or shared memory, some memory regions have additional

access constraints, and some regions are subdivided, as Table 12 shows:

2.2.5

Software ordering of memory accesses

The order of instructions in the program flow does not always guarantee the order of the cor-

responding memory transactions. This is because:

•

The processor can reorder some memory accesses to improve efficiency, providing this

does not affect the behavior of the instruction sequence.

•

Memory or devices in the memory map might have different wait states.

•

Some memory accesses are buffered or speculative.

Memory system ordering of memory accesses on page 21 describes the cases where the

memory system guarantees the order of memory accesses. Otherwise, if the order of mem-

ory accesses is critical, software must include memory barrier instructions to force that

ordering. The processor provides the following memory barrier instructions:

Table 12. Memory region shareability and cache policies

Address range

Memory region

Memory type(1)

1. See 2.2.1: Memory regions, types and attributes on page 20 for more information.

Shareability(1)

Cache policy(2)

2. WT = Write through, no write allocate. WBWA = Write back, write allocate.

0x00000000-

0x1FFFFFFF

Code

Normal

0x20000000-

0x3FFFFFFF

SRAM

Normal

WBWA

0x40000000-

0x5FFFFFFF

Peripheral

Device

0x60000000-

0x7FFFFFFF

External RAM

Normal

WBWA

0x80000000-

0x9FFFFFFF

0xA0000000-

0xBFFFFFFF

External device

Device

Shareable

0xC0000000-

0xDFFFFFFF

Non-shareable

0xE0000000-

0xE00FFFFF

Private Peripheral

Bus

Strongly- ordered

Shareable

0xE0100000-

0xFFFFFFFF

Device

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