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LT1246CS8 Datasheet(PDF) 7 Page - Linear Technology

No. de pieza LT1246CS8
Descripción Electrónicos  1MHz Off-Line Current Mode PWM and DC/DC Converter
PDF  12 Pages
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Fabricante Electrónico  LINER [Linear Technology]
Página de inicio  http://www.linear.com
Logo LINER - Linear Technology

LT1246CS8 Datasheet(HTML) 7 Page - Linear Technology

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7
LT1246/LT1247
GND (Pin 5): Ground.
OUTPUT (Pin 6): Current Output. This pin is the output of
a high current totem pole output stage. It is capable of
driving up to
±1A of current into a capacitive load such as
the gate of a MOSFET.
VCC (Pin 7): Supply Voltage. This pin is the positive supply
of the control IC.
VREF (Pin 8): Reference. This is the reference output of the
IC. The reference output is used to supply charging current
to the external timing resistor RT. The reference provides
biasing to a large portion of the internal circuitry, and is
used to generate several internal reference levels includ-
ing the VFB level and the current sense clamp voltage.
PI
FU C
S
TI
S
APPLICATI
I FOR ATIO
deadtime at that frequency. Curves of oscillator frequency
and deadtime for various values of RT and CT appear in the
Typical Performance Characteristics section. Frequency
and deadtime can also be calculated using the following
formulas:
Oscillator Rise Time: tr = 0.583 • RC
Oscillator Discharge Time:
Oscillator Period: tOSC = tr + td
Oscillator Frequency:
Maximum Duty Cycle:
The above formulas will give values that will be accurate
to approximately
±5%, at the oscillator, over the full
operating frequency range. This is due to the fact that the
oscillator trip levels are constant versus frequency and the
discharge current and initial oscillator frequency are
trimmed. Some fine adjustment may be required to achieve
more accurate results. Once the final RT/CT combination is
selected, the oscillator characteristics will be repeatable
from device to device. Note that there will be some slight
differences between maximum duty cycle at the oscillator
and maximum duty cycle at the output due to the finite rise
and fall times of the output.
Error Amplifier
The LT1246/LT1247 contain a fully compensated error
amplifier with a DC gain of 90dB and a unity-gain fre-
quency of 2MHz. Phase margin at unity-gain is 80
°. The
noninverting input is internally committed to a 2.5V refer-
ence point derived from the 5V reference of pin 8. The
Minimum
Start-Up
Operating
Maximum
Device
Threshold
Voltage
Duty Cycle
Replaces
LT1246
16V
10V
100%
UC1842
LT1247
8.4V
7.6V
100%
UC1843
Oscillator
The LT1246/LT1247 are fixed frequency current mode
pulse width modulators. The oscillator frequency and the
oscillator discharge current are both trimmed and tightly
specified to minimize the variations in frequency and
deadtime. The oscillator frequency is set by choosing a
resistor and capacitor combination, RT and CT. This RC
combination will determine both the frequency and the
maximum duty cycle. The resistor RT is connected from
VREF (pin 8) to the RT/CT pin (pin 4). The capacitor CT is
connected from the RT/CT pin to ground. The charging
current for CT is determined by the value of RT. The
discharge current for CT is set by the difference between
the current supplied by RT and the discharge current of the
LT1246/LT1247. The discharge current of the device is
trimmed to 8.2mA. For large values of RT discharge time
will be determined by the discharge current of the device
and the value of CT. As the value of RT is reduced it will have
more effect on the discharge time of CT. During an oscil-
lator cycle capacitor CT is charged to approximately 2.8V
and discharged to approximately 1.1V. The output is
enabled during the charge time of CT and disabled, in an
off state, during the discharge time of CT. The deadtime of
the circuit is equal to the discharge time of CT. The
maximum duty cycle is limited by controlling the deadtime
of the oscillator. There are many combinations of RT and
CT that will yield a given oscillator frequency, however
there is only one combination that will yield a specific
t
RC
R
d =
346
0 0164
11 73
.
..
f
t
OSC
OSC
=
1
D
t
t
tt
t
MAX
r
OSC
OSC
d
OSC
==



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