LTC1645CS datasheet(14/24 Pages) LINER

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LTC1645

An external hard reset is initiated at time point 6. The ON

pin is forced below 0.8V but above 0.4V, and the GATE

pin voltages start to ramp down. VOUTn also starts to ramp

down, and RESET goes low when VOUT2 drops below the

power-good trip level at time point 7.

Time points 8 to 15 are similar to time points 1 to 7, except

the ON pin’s different voltage thresholds are used to ramp

VOUT1 and VOUT2 separately. At time point 8, the ON pin

goes above 0.8V but below 2V, and one timing cycle later

(time point 9) GATE1 begins to ramp up with VOUT1

following one gate-to-source voltage drop lower. At time

point 10, the ON pin goes above 2V and GATE2 immedi-

ately begins ramping up with VOUT2 following one gate-to-

source voltage drop lower. As soon as VOUT2 reaches its

power-good trip level at time point 11, a timing cycle

starts. At the end of the timing cycle (time point 12),

RESET goes high and the power-up process is complete.

The ON pin is forced below 2V but above 0.8V at time point

13 and the GATE2 pin voltage starts to ramp down. VOUT2

also starts to ramp down and RESET goes low when VOUT2

drops below the power-good trip level at time point 14.

When the ON pin goes below 0.8V but above 0.4V at time

point 15, GATE1 and VOUT1 ramp down.

Time points 16 to 19 show the same power-up sequence

as time points 2 to 5, while time point 20 demonstrates the

GATE

n pins being pulled immediately to ground (instead

of ramping down) by the ON pin going below 0.4V.

Power Supply Tracking and Sequencing Applications

The LTC1645 is able to sequence VOUTn in a number of

ways, including ramping VOUT1 up first and down last;

ramping VOUT1 up first and down first; ramping VOUT1 up

first and VOUT1 and VOUT2 down together; and ramping

VOUT1 and VOUT2 up and down together.

Figure 15 shows an application ramping VOUT1 and VOUT2

up and down together. The ON pin must reach 0.8V to

ramp up VOUT1 and VOUT2. The spare comparator pulls the

ON pin low until VCC2 is above 2.3V, and the ON pin cannot

reach 0.8V before VCC1 is above 3V. Thus, both input

supplies must be within regulation before a timing cycle

can start. At the end of the timing cycle, the output voltages

ramp up together. If either input supply falls out of

regulation, the gates of Q1 and Q2 are pulled low together.

Figure 16 shows an oscilloscope photo of the circuit in

Figure 15.

APPLICATIO S I FOR ATIO

Figure 15. Ramping 3.3V and 2.5V Up and Down Together

1/2 Si4920DY

0.01

Ω*

0.01

Ω*

Ω

1.18k

10k

1.37k

0.1

µF

25V

0.33

µF

*WSL1206-01-1% (VISHAY DALE)

CLOAD1

CLOAD2

1N4002

MBR0530T1

1N4002

BOTH CURRENT LIMITS: 5A

VCC1

FAULT

TIMER

GND

SENSE1

GATE2

GATE1

VCC2

TRIP

POINT:

VIN1

3.3V

VIN2

2.5V

VOUT1

3.3V

2.5A

VOUT2

2.5V

2.5A

µP RESET

LTC1645

(14-LEAD)

COMP+

COMPOUT

SENSE2

1645 F15

RESET

1.18k

4.99k

10k

1.37k

1.82k

LTC1645CS Datasheet(PDF) 14 Page - Linear Technology

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