LTC1665IGN datasheet(9/16 Pages) LINER

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LTC1665/LTC1660

Figure 2a. LTC1665 Register Loading Sequence

OPERATIO

Table 1a. LTC1665 Input Word

DIN

DOUT

SCK

CS/LD

INPUT WORD W0

INPUT CODE

1665/60 F02a

(ENABLE CLK)

(UPDATE OUTPUT)

ADDRESS/CONTROL

DON’T CARE

INPUT WORD W0

INPUT WORD W–1

DIN

DOUT

SCK

CS/LD

INPUT WORD W0

INPUT CODE

DON’T CARE

1665/60 F02b

(ENABLE CLK)

(UPDATE OUTPUT)

ADDRESS/CONTROL

INPUT WORD W0

INPUT WORD W–1

Figure 2b. LTC1660 Register Loading Sequence

A3 A2 A1

Address/Control

A0 D7 D6 D5 D4 D3 D2 D1 D0 X3

X1 X0

Don’t Care

Input Code

A3 A2 A1

Address/Control

A0 D9 D8 D7 D6 D5 D4 D3 D2 D1

X1 X0

Input Code

Don’t

Care

Table 1b. LTC1660 Input Word

chips in the chain. In use, CS/LD is held low while

16-bit words are clocked to DIN of the first chip; CS/LD is

then pulled high, updating all of them simultaneously.

Sleep Mode

DAC address 1110b is reserved for the special Sleep

instruction (see Table 2). In this mode, the digital interface

stays active while the analog circuits are disabled; static

power consumption is thus virtually eliminated. The refer-

ence input and analog outputs are set in a high impedance

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