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RFDA0045

DS110621

7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical

support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.

Serial Port Interface

SPI Timing Diagram Specifications

Truth Table

Parameter

Limit

Unit

Comment

t1

25

MHz max

CLK Frequency

t2

20

ns min

CLK High

t3

20

ns min

CLK Low

t4

5

ns min

DATA to CLK Setup Time

t5

5

ns min

DATA to CLK Hold Time

t6

30

ns min

DATA Valid

t7

5

ns min

LE to CLK Setup Time

t8

5

ns min

CLK to LE Setup Time

t9

10

ns min

LE Pulse Width

t10

20

ns max

Output Set

Control Bit

Gain Relative to Maximum Gain

D5

D4

D3

D2

D1

D0

1

11111

0dB

1

11110

-0.5dB

1

11101

-1dB

1

11011

-2dB

1

10111

-4dB

1

01111

-8dB

0

11111

-16dB

0

00000

-31.5dB

Power-up Programming Truth Table

Logic Voltage Levels

PUP

Attenuator Setting

State

Logic

High

Attenuation at min, 0dB

Low

0V to 0.8V

Low

Attenuation at max, 31.5dB

High

2.0V to 5.0V

CLK

DATA

LE

DOUT

SPI Timing Diagram

Programming Example, 6-Bit

MSB

LSB

D4

D3

D2

D0

D1

D5

CLK

DATA

LE