SPI/Microwire-Compatible

UART in QSOP-16

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9

POR

STATE

DESCRIPTION

0000

0000

X

Pr

r

Receive-Parity Bit. This bit is the extra bit received if PE = 1. Therefore, PE = 1 results in 9-bit

transmissions (L = 0). If PE = 0, then Pr is set to 0. Pr is stored in the FIFO with the receive

data (see the

Nine-Bit Networks section).

0

0

IR

r

Reads the value of the IR bit.

L

READ/

WRITE

w

B0–B3

w

Baud-Rate Divisor Select Bits. Sets the baud clock’s value (Table 6).

B0–B3

r

Baud-Rate Divisor Select Bits. Reads the 4-bit baud clock value assigned to these registers.

BIT

NAME

Bit for setting the word length of the transmitted or received data. L = 0 results in 8-bit words

(9-bit words if PE = 1), see Figure 5. L = 1 results in 7-bit words (8-bit words if PE = 1).

0

X

L

r

Reads the value of the L bit.

Pt

w

Transmit-Parity Bit. This bit is treated as an extra bit that will be transmitted if PE = 1. To be

useful in 9-bit networks, the MAX3100 does not calculate parity. If PE = 0, then this bit (Pt) is

ignored in transmit mode (see the

Nine-Bit Networks section).

00000000

0

D0r–D7r

r

Eight data bits read from the receive FIFO or the receive register. These will be all 0s when

the receive FIFO or the receive registers are empty. When L = 1, D7r is always 0.

FEN

w

FIFO Enable. Enables the receive FIFO when FEN = 0. When FEN = 1, FIFO is disabled.

0

0

FEN

r

FIFO-Enable Readback. FEN’s state is read.

IR

w

Enables the IrDA timing mode when IR = 1.

No

change

X

CTS

r

Clear-to-Send-Input. Records the state of the CTS pin (CTS bit = 0 implies CTS pin = logic

high).

D0t–D7t

w

Transmit-Buffer Register. Eight data bits written into the transmit-buffer register. D7t is ignored

when L = 1.

Table 5. Bit Descriptions

0

PE

w

Parity-Enable Bit. Appends the Pt bit to the transmitted data when PE = 1, and sends the Pt

bit as written. No parity bit is transmitted when PE = 0. With PE = 1, an extra bit is expected to

be received. This data is put into the Pr register. Pr = 0 when PE = 0. The MAX3100 does not

calculate parity.

0

PE

r

Reads the value of the Parity-Enable bit.

0

PM

w

Mask for Pr bit. IRQ is asserted if PM = 1 and Pr = 1 (Table 6).

0

PM

r

Reads the value of the PM bit (Table 6).

0

R

r

Receive Bit or FIFO Not Empty Flag. R = 1 means new data is available to be read from the

receive register or FIFO.

0

RM

w

Mask for R bit. IRQ is asserted if RM = 1 and R = 1 (Table 6).

0

RM

r

Reads the value of the RM bit (Table 6).

0

RAM

w

Mask for RA/FE bit. IRQ is asserted if RAM = 1 and RA/FE = 1 (Table 6).

0

RAM

r

Reads the value of the RAM bit (Table 6).

0

RTS

w

Request-to-Send Bit. Controls the state of the RTS output. This bit is reset on power-up (RTS

bit = 0 sets the RTS pin = logic high).