Low-Voltage, CMOS Analog Multiplexers/Switches

with Enable Inputs and Address Latching

14

______________________________________________________________________________________

_________________________________Test Circuits/Timing Diagrams (continued)

Figure 7. Setup and Hold Times, Minimum

LE Width

V-

COM

V-

300

Ω

GND

ADDC

ADDB

ADDA

LE

50

Ω

50

Ω

35pF

EN1

V+

V+

MAX4530

NO1–NO7

+3V

NO0

V- = 0V FOR SINGLE-SUPPLY OPERATION.

REPEAT TEST FOR EACH SECTION.

0V

0V

3V

90%

50%

50%

3V

3V

0V

EN2

V-

COM_

V-

300

Ω

GND

ADDA

ADDB

LE

50

Ω

50

Ω

35pF

EN1

V+

V+

MAX4531

NO1_, NO2_, NO3_

+3V

NO0_

EN2

V-

COM_

V-

300

Ω

GND

ADD_

LE

50

Ω

50

Ω

35pF

EN1

V+

V+

MAX4532

NO_

+3V

NC_

EN2